Inaccurate timer synchronization problem

[nimamoaddabi]

Posted on November 18, 2015 at 06:54

Hi everybody,

I need to synchronise Timer1 and timer4 to each other, in my STM32F103.These slave timers are Triggered by Timer2 as Master timer. I even set the MSM bit of TIM2_SMCR to have better synchronization.I use PLL clock set to 36MHz as System clock. Timers clock frequency are also 36MHz.The prescalers of both Timer1 and Timer4 are set to 0, while their ARR are same, e.g. 1800.As I check in debug mode, both Timer 1 and Timer4 are started at the same time but their counter values diffrent from each other. Can anybody help me on this problem? #stm32-timers

[Tesla DeLorean]

Posted on November 18, 2015 at 14:58

Is there a question here?

[nimamoaddabi]

Posted on November 18, 2015 at 18:07

Sorry, I don't know why the body of my question was not shown. I editted it again.

[ftiti]

Posted on November 18, 2015 at 18:30

Hello Nima,

It's normal since you debug and  the counter of timer still counting. To debug correctly TIM1 and TIM4 processing you should set the corresponding debug bist in the debug MCU freeze registesr: DBG_TIM1_STOP (

DBGMCU_APB2_FZ register)

DBG_TIM4_STOP. (

DBGMCU_APB1_FZ register)

[ All for one and one for all]

[nimamoaddabi]

Posted on November 18, 2015 at 19:27

Thank you very much tn.metalfun

I will test it, hope it works correctly by setting debug bits. For your information: In my last tests, I checked the the value of counters in Watch windows (e.g. by writing TIM1->CNT and TIM4->CNT). When I put some break points in my codes to stop time progressing, the value of counters in Watch window also stops. In this point, I checked the value of counters in Watch window and I saw that they are different. This was strange for me. Hope by setting Debug stop bits, the problem can be solved.