BUG: STM32Cube_FW_H5_V1.3.0 - HAL_RCCEx_GetPLL2ClockFreq() reports incorrect frequency when FRACN mode enabled.

[ebrombaugh1]

HAL_RCCEx_GetPLL2ClockFreq() computes the frequency of the three outputs of PLL2. When PLL2 is in Fractional N mode it reports wildly inaccurate frequencies which can affect the setup of other peripherals like the SPI/I2S port.

The problem is that the PLL2 code seems to have been ported from another PLL without correcting bit positions. The pll2fracen variable contains the value of the RCC_PLLCFGR_PLL2FRACEN and is used to multiply another value by 0 or 1, but it has not been shifted down to bit position 0, so the multiplication ends up scaling incorrectly.

line 2986 of stm32h5xx_hal_rcc_ex.c reads as

 pll2fracen = RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2FRACEN;

but should be

 pll2fracen = (RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2FRACEN) >> RCC_PLL2CFGR_PLL2FRACEN_Pos;

Hope that helps.

Eric

PS - this bug report is almost identical to one I submitted against the H7 HAL about 5 years ago! Seems that this problem is getting copied around without getting fixed. See it here:

https://community.st.com/t5/stm32-mcus-embedded-software/bug-stm32cube-fw-h7-v1-5-0-hal-rccex-getpll3clockfreq-reports/m-p/313421

[STTwo-32]

Hello @ebrombaugh1 

Thank you so much for reporting this. I 've escalated this issue internally for correction (under internal ticket number 190435).

PS: Same problem on the HAL_RCCEx_GetPLL2ClockFreq() & HAL_RCCEx_GetPLL3ClockFreq().

Best Regards

STTwo-32