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in STM32G474 , Increasing the PLL frequency to 160Mhz (max allowable) make the core lock up and the core frequency can be increead to 160MHz only if AHB is prescaled

AIBRA.1
Associate II
 
6 REPLIES 6
gbm
Lead III

Check internal power supply settings and Flash wait states.

My STM32 stuff on github - compact USB device stack and more: https://github.com/gbm-ii/gbmUSBdevice

I performed these steps appended in the data sheet but during debugging the program comes to write to FLASH_ACR to adjust the number of flash wait states and gives Target is not responding.

Thank you.

0693W00000Y8G0JQAV.png0693W00000Y8FzVQAV.png 

gbm
Lead III

Is PWR module enabled?

My STM32 stuff on github - compact USB device stack and more: https://github.com/gbm-ii/gbmUSBdevice

I enabled the clock for Both PWR and Flash interface before Clock Configuration and the problem appears at assigning wait states to Flach_ACR register by showing the target does not respond during the debug session.

0693W00000Y8G4QQAV.png

gbm
Lead III

By using magic numbers instead of named constants and multiple statements to set a single register you are asking for trouble. Why not:

RCC_>AHB2ENR |= RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOBEN | RCC_AHB2ENR_GPIOCEN;

Also, FLASH->ACR register contains some important bits set by default. So, to set wait states without turning off the debug interface, use:

FLASH->ACR |= 4u;

My STM32 stuff on github - compact USB device stack and more: https://github.com/gbm-ii/gbmUSBdevice
AIBRA.1
Associate II

Thank you so much