2022-09-13 08:06 PM
Hi All,
I have a STM32H7 master communicating with I2C to 4 STM32F0 slaves. The I2C uses DMA but intermittently stalls when the master is transmitting to a slave. It sends the address and the first data byte successfully (acknowledged), but then fails to transmit the second data byte and the clock is held low. No errors are returned, but the driver waits indefinitely for the transmission to complete (which it never does). There is a screenshot of the bus stalling attached.
Note, the I2C buffers have been located in non-cached memory and is accessible by DMA.
Is anyone aware of any issues with transmitting I2C using DMA?
Kind Regards
David
Solved! Go to Solution.
2022-10-05 05:35 PM
Hi @F.Belaid,
The issue has been fixed. The root cause was a defect in the STM32H743 silicon. The defect is included in the errata of other microprocessors, but not in the STM32H743 errata. However, STM has confirmed the STM32H743 does contain the same defect and they will update the errata in mid October.
In the meantime, you can view the defect description in the STM32H723 errata (section 2.16.4):
The workaround was to change the I2C kernel clock frequency so the ratio was not between 1.5 and 3.0.
Cheers
David
2022-10-05 03:39 AM
Hi @DOsbo ,
I was wondering if you still have the issue? If yes, can you state the flag errors of each slave ?
Have you tried to communicate with each slave separately? If yes, verify the address of each slave to be sure frequencies are working fine.
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2022-10-05 05:35 PM
Hi @F.Belaid,
The issue has been fixed. The root cause was a defect in the STM32H743 silicon. The defect is included in the errata of other microprocessors, but not in the STM32H743 errata. However, STM has confirmed the STM32H743 does contain the same defect and they will update the errata in mid October.
In the meantime, you can view the defect description in the STM32H723 errata (section 2.16.4):
The workaround was to change the I2C kernel clock frequency so the ratio was not between 1.5 and 3.0.
Cheers
David