How to use FMC in main while loop and interruption at the same time correctly?

[User16583013529283943681]

Hello everyone. I am using STM32H743IIT with a sensor and two external SRAMs. The sensor is connected to the STM32H743x by SPI5 and EXIT2. The external SRAMs are connected to the STM32H743x by FMC.

The sensor triggers the EXIT2 and in the interrupt function data will be received by SPI and saved to the first external SRAM in sequence.

In the main while loop, every 20ms(counted by the number of data point), the data in the first external SRAM will be replicated to the second SRAM in sequence. Then a comparation of the data between the source and the destination will run to check.

The check result is that some data are different which means something wrong in the replication progress if the external interruption is enabled during the replication and the comparation. But if the external interruption is disabled during the replication and the comparation the check result is that all the data are the same between the source and the destination.

I want to know how to solve the problem so that I can save the data from the sensor continuously and also using the data saved in the external SRAMs correctly.

Thanks a lot.

[Tesla DeLorean]

Sounds like you need to focus on what the EXTI ​and related interrupt and callback are actually doing, and the memory/structures they are touching. Or if they are taking too long.

Are appropriate variables volatile?​

[User16583013529283943681]

Thanks for your attention.

Sorry I missed some details. In the interruption function, it only call the API to start SPI transfer in DMA mode and it's over. The data saving progress are in the SPI callback function. But you are right I need try to minimize the time-cost in the interruption and callback.

The related variables are defined as volatile.

I think the cause of this mistake is that the priority of the interruption or the callback function is higher which means the access to the external SRAM by FMC could be broken and FMC might be used to access to the external SRAM for another value. But FMC does not have something like a stack which could used to push and pop to protect the context. In this situation, something wrong may happened during replication.

If the RTOS is not in the consideration, is there anything to solve the problem?

Looking forward to your suggestions.😀

[Pavel A.]

So are you saying that you compare the data while DMA overwrites it in background? Really? Do you enable the D-cache, by the way?

[Tesla DeLorean]

I'd start by assuming the FMC/BUS are solid. Check the Errata.

Things that will give you headaches are CACHE COHERENCY, and how the MCU treats the memory it shows you (ConfigMPU, etc)

The caching is done on 32-byte lines, make sure all buffering and inspection is suitably aligned.