How to flush SPI buffer when using SPI over DMA.

[SDas.1]

I am using STM32G071RBTx on our custom boards. The controller is connected to a Beaglebone Black over SPI. The STM32 controller is working as an SPI slave and the Beaglebone as the master. There are not CS lines defined for the communication. FreeRTOS with CMSIS_V2 is used as middleware. The highest priority task polls the SPI lines over DMA for any incoming command. Sometimes the SPI messages are not in sync. They get shifted by a few bytes and a flush of the buffer is required. I am trying to use the HAL_SPIEx_FlushRxFifo API to flush the Rx buffer for any out of sync message. But it does not seem to work. I don't know if it works when I am using SPI over DMA? Any suggestions on how to flush the SPI is welcome.

[TDK]

HAL_SPIEx_FlushRxFifo reads all pending data in the DR register.

https://github.com/STMicroelectronics/STM32CubeG0/blob/5cb06333a6a43cefbe145f10a5aa98d3cc4cffee/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_spi_ex.c#L80

Since you are using DMA, there should not be any data in there, and the function won't do anything useful.

If your bytes are out of sync, reading and discarding everything already received in software will get things back in line.

I suspect there is some higher level error in logic which is causing your out of sync errors. Since SPI sends and received exactly at the same time, there should not be an opportunity for things to become out of sync.

Since the STM32 is the slave, data needs to be ready to be sent out prior to the master clocking data. If you already sent data to DR, you will need to stop and restart the transfer in order to clear this data without any action by the master.

[SDas.1]

Yes, I also think there is higher level logical error. I wanted to flush the buffer just as a recovery mechanism. I will investigate further into why the messages are sometimes out of sync. Thanks for the reply