How to detect end of SPI transmission?

[toby2]

Posted on December 20, 2017 at 13:27

STM32F030.

I am transmitting multiple words via spi to some shift registers and need to latch the shift registers when the transmission of the last word is finished. The latch signal is GPIO. Device is master.

I don't want to block or poll for SPI busy.

The only way I can think to do this is to to use duplex and count (and discard) the receive bytes. Is there a better way?

TIA.

Toby

#stm32f030-spi #transmission #spi

[AvaTar]

Posted on December 20, 2017 at 13:29

Perhaps you can use the SlaveSelect (NSS) signal to latch ?

[toby2]

Posted on December 20, 2017 at 13:30

Sorry, to clarify, I am doing this under interrupts.

[S.Ma]

Posted on December 20, 2017 at 13:47

In the RNXE interrupt once the last byte has been transmitted, toggle the latch signal. No wait, set the interrupt on this event when it is needed. Make sure the RXNE behaviour is well set (in case of FIFO SPI IP)

Otherwise, more acrobatic and HW assisted, if the SPI block transfer is done by DMA, the block transfer duration is predictable: You could use a timer output compare from the start of block transmit. Another output compare from the same timer could generate the NSS rise edge without any interrupt at all....

[toby2]

Posted on December 20, 2017 at 13:52

Perhaps I could, if the guy who designed the board had used the right pin

Unfortunately I only have a GPIO so it has to be software driven.

[toby2]

Posted on December 20, 2017 at 14:00

KIC8462852 EPIC204278916 wrote:

In the RNXE interrupt once the last byte has been transmitted, toggle the latch signal. No wait, set the interrupt on this event when it is needed. Make sure the RXNE behaviour is well set (in case of FIFO SPI IP)

Not sure I follow this last bit. Are you suggesting only setting SPI_CR2_RXNEIE when I write the last word to the TX buffer? Would that not just cause an overflow on the previous words? Or is it possible to turn on RX half while the SPI is busy?

KIC8462852 EPIC204278916 wrote:

Otherwise, more acrobatic and HW assisted, if the SPI block transfer is done by DMA, the block transfer duration is predictable: You could use a timer output compare from the start of block transmit. Another output compare from the same timer could generate the NSS rise edge without any interrupt at all....

I like that idea. I think my LATCH gpio is also a timer output. 

[S.Ma]

Posted on December 20, 2017 at 19:13

You are supposed to have read the SPI DR before writing something to send something out.

When you write the last byte, enable the interrupt for RXNE. 

In master mode, the TXE triggers at the beginning of the SCK first clock pulse

the RXNE will trigger when the byte has been fully received.

Usually I only use RXNE interrupt for SPI master... usually with DMA block transfer.

[AVI-crak]

Posted on December 20, 2017 at 21:10

In cyclic mode, you can use two timers to simulate external NSS and SCK. SPI in slave mode using DMA.

This scheme will work if there is a priority for the DMA. The smallest memory access fault will trigger a chain reaction of destruction.I use a similar scheme to expand external ports.You should provide a procedure for stopping transmission without damaging external information. For example, use the NRST line from the st-chip to initialize the external extension to zero state.

The best option is interruption.

[toby2]

Posted on December 20, 2017 at 21:06

Thanks, I think I understand now.

Thinking about it more I think I will use your idea of DMA for the transfer and a timer to trigger the latching. I have some other activity that needs to syncronise to the spi transfer that would work well from a timer interrupt.

[toby2]

Posted on December 20, 2017 at 21:43

avi_crak.videocrak wrote:

In cyclic mode, you can use two timers to simulate external NSS and SCK. SPI in slave mode using DMA.

Taking each bit at a time to make sure I understand.....

I think I understand what you suggest but in my case I don't think I need to worry about this. I am the master and the slave is a simple shift register with latch signal. So as long as I clock data out at a known speed I am ok.

avi_crak.videocrak wrote:

This scheme will work if there is a priority for the DMA. The smallest memory access fault will trigger a chain reaction of destruction.

hmm... I have not thought about DMA priority or memory access faults. If this spi port is the only thing using DMA should I be concerned?

(I have used DMA very rarely)

avi_crak.videocrak wrote:

You should provide a procedure for stopping transmission without damaging external information. For example, use the NRST line from the st-chip to initialize the external extension to zero state.

Again, I *think* I am ok here as I do not need to reset the slave. It is enough that on the next transmission the correct data gets sent.

avi_crak.videocrak wrote:

The best option is interruption.

I am not sure I understand this. Are you saying it is better to use interrupts rather than DMA? If so, can you explain why?

Thanks

Toby