How to clear the SPI RX FIFO (register mode)

[Roshan]

Hi all,

I have an issue. I need to see the Slaves free space, for that, I am reading the slave's Empty space, and based on the results I send the data points which needed. but I am having a big issue. it always has a one execution cycle delay.

For example, if read empty spaces as 100, then code is sending 80 data plots which is regarded to the previous read. I am quite confused.

GPIOA->BSRR = GPIO_BSRR_BR4;	 //CS low
 
SPI1->DR = 0xF012;               // Send read value command
 while(!(SPI1->SR & SPI_SR_TXE)) {}             // wait for TX end
RX_FIFO= SPI1->DR;            // read the empty values in RX fifo
GPIOA->BSRR = GPIO_BSRR_BS4;   // Cs high
 
*
*
*
GPIOA->BSRR = GPIO_BSRR_BR4;	 //CS low
// then send the data required according to RX_FIFO (for loop is used to send data)
GPIOA->BSRR = GPIO_BSRR_BS4;   // Cs high

This happens in every 50KHz interrupt, I tried to keep an interval in between sending and receiving, but still the same problem if anyone go this issue. please help me. I think this might be due to masters Rx is not clearing up. Does anybody know how to clear the Masters Rx in register mode? I can't use HAL because it consumes a lot of time.

Thanks

[TDK]

> Does anybody know how to clear the Masters Rx in register mode?

I see you tagged the post with both STM32F4 and STM32F7.

The F4 doesn't have an RXFIFO and you simply read DR to clear incoming data.

The F7 has an RXFIFO and you need to read DR enough to clear it out. If you don't care about the data, a single 32-bit read should work.

I doubt that's the issue here, however. Guessing, as there isn't much code to go from.

[waclawek.jan]

Which STM32?

If you read SPI_DR before SPI_SR.RXNE is set, the received value remains in the buffer/FIFO. In other words, check SPI_SR.RXNE before you read SPI_DR.

JW

[S.Ma]

If you are a master, you must wait for receive bytes, make your waits based on RXNE and not TXE

TXE will be set as soon as you write a byte to transmit ! Even before the SPI clock toggles!

And when the same amount of transmitted bytes will be received and you should read them all from the RX FIFO.

You can read more bytes from the RX FIFO to "empty" it, if necessary.

The SPI Slave mode of operation is more... tricky.

[waclawek.jan]

> Even before the SPI clock toggles!

Although not important in context of this thread, this detail is not entirely true, at least not in this particular case, where TXE was seen being set after first bit has been transmitted.

> The SPI Slave mode of operation is more... tricky.

It's true that it's not entirely clear, whether the STM32 is master or slave here.

JW