How much current ripple is allowable in a VDD (and/or VDDA) = 3.3V power supply for an STM32?

Strictly speaking you should be asking how much ripple voltage is tolerable at the Vdd and VddA pins.

Microcontrollers, indeed any digital CMOS, do not consume constant current. Instead take significant gulps of current for tiny durations (perhaps it is better to imagine they take gulps of charge), typically on every internal clock edge. The amount of each gulp depends on what processing is being done.

No voltage-regulator can respond fast-enough to these gulps. Indeed a few centimetres of pcb track has too much inductance to allow correct operation. So we put decoupling capacitors on every power-supply-pin pair on the stm32 package. The data sheet recommends 100 nF ceramic on each Vdd/Vss pair and one 4.7uF (could be tantalum or ceramic) - see the section on "power supply scheme".

These gulps are much bigger than likely ripple in a switch-mode regulator.

Ripple voltage might also affect the PLL oscillator stability but I haven't seen any data on that.

I have successfully used a TPS82150 switching-regulator module (built-in inductor) with 22 uF as the big decoupler and however many 100 nF.

As for VddA, ripple will have a direct bearing on ADC accuracy. So additional filtering is useful. Current drain might be sufficiently low that RC filtering is tolerable here. In my case I used 0.1 ohm and 10 uF.

Hope this helps,

Danish

The mcu's internal logic is powered through its own internal LDO.

JW

Recently, there was a thread on the STM32G4's ADC. The key takeaway for me was that Vref requires a low source impedance because during the conversion they need bursts of current. AN5346 talks about some of the requirements.

The Nucleo board schematic and the AN5346 schematic show an inductor with a short to bypass it - which tells me try it both ways and pick the one that works better.