Hello, I have a question regarding the Flash Bank organization of the STM32F4xx Devices (we use STM32F469IG with 1MB Flash).

[Andreas Zeiler]

This MCU has 1MB Flash which can be configured with the DB1M Bit in the OPTCR Regs of Flash Controller.

Default is DB1M=0, which layouts the flash in single bank mode in 12 Sectors.

DB1M=1 layouts the flash in dual bank mode with 2x 8 Sectors.

When DB1M=0 is selected, will the flash get accessed physically over 1 bank or still over bank 1 and bank 2.

To be more detailed, I'm interested in one point. When DB1M = 0 , does a write on the least 512kB flash sectors will stall the cpu (because then the cpu is not able to fetch instructions anymore)?

2 years ago I made some tests with 2 banked Flash but on 2Mbyte devices. Writing on Bank 1 while executing code from Bank 0 was no Problem and didn't stall the cpu. Writing on Bank 0 while executing from Bank 0 stalled the CPU.

We want to use the 2nd flash bank for persistent config data, etc. No exec code.

Thnaks.

Kind regards

Andreas

[Piranha]

My guess is that it works like single bank and will stall the CPU.

But I will remind another aspect. Each flash write operation takes 16 us and, if you implement it with CPU (not DMA), then between each write operation CPU can process interrupts and in a case of RTOS also all higher priority tasks. It should be "real time" enough for the most of devices.

[Andreas Zeiler]

Hello,

thanks for your answer. We use an RTOS and will consider that. In my tests I got the same timings for writing into flash.

I discussed this with ST Support and they replied that the MCU we use (STM32F469IGH6) supports Read-While-Write (RWW) when the DB1M Bit is set.

[Ozone]

If it is set to dual bank mode, writing to one bank is not supposed to stall execution from the other.

That is the meaning of the term "bank" in this context.