2023-06-08 10:10 PM - edited 2023-11-20 03:36 AM
All data received in normal mode is 0, but some correct data can be received in debug mode?
cubemx configurations are as follows:
uint8_t pData[128] = {0x00};
HAL_SPI_Receive_DMA(&hspi1,pData,128);
while(HAL_SPI_GetState(&hspi1) != HAL_SPI_STATE_READY);
while(CDC_Transmit_FS(pData,128) != USBD_OK);
while(CDC_Transmit_FS(TestData,1) != USBD_OK); //0xff
The monitor variable is indeed the same as displayed after receiving by the upper computer, again proving that the upper computer has no problem with USB transmission.
Questions:
Thanks for your suggestions and reply.
There is original address:https://shequ.stmicroelectronics.cn/thread-640472-1-1.html
Solved! Go to Solution.
2023-06-13 12:20 AM
yepp. :)
very basic standard problem: dma and cpu are both "master" on internal bus+memory ;
when D-cache buffers data, it is buffering memory wherever it could "help" the cpu to get without wait cycles the variables or data.
now dma writing some data in memory - but cache controller can not know about this action. So you get possibility memory has new data, but cpu still see "old" data in cache (for same adress).
simple solution: switch off D-cache.
perfect: use MMU or cache management ("invalidate cache" etc. ) to let the cache controller know, what memory areas are or maybe invalid.
2023-06-09 12:22 AM
I see no cache management, so try: switch off D-cache , then try again.
2023-06-09 12:26 AM
How to switch off D-cache? I use this function
// /* Enable I-Cache---------------------------------------------------------*/
SCB_EnableICache();
// /* Enable D-Cache---------------------------------------------------------*/
SCB_EnableDCache();
in main.c.Is it?
2023-06-09 01:13 AM
Thanks you.it could recevie data normally after I remove SCB_EnableDCache().
2023-06-11 06:12 PM
Could I ask why it has to do with D-cache?
2023-06-13 12:20 AM
yepp. :)
very basic standard problem: dma and cpu are both "master" on internal bus+memory ;
when D-cache buffers data, it is buffering memory wherever it could "help" the cpu to get without wait cycles the variables or data.
now dma writing some data in memory - but cache controller can not know about this action. So you get possibility memory has new data, but cpu still see "old" data in cache (for same adress).
simple solution: switch off D-cache.
perfect: use MMU or cache management ("invalidate cache" etc. ) to let the cache controller know, what memory areas are or maybe invalid.