GPIO state at power down

[Lukasz Przenioslo]

Posted on February 03, 2018 at 23:40

Hello there,

According to the datasheet, the GPIO ports circuit diagram looks like this in STM323L4x2:

From this diagram I understand that at powerdown (VCC = VSS = 0 V) the I/O pin state is high impedance. But is that 100% correct? I want to make sure before I make a design move that would save me some components. But for this I need to know either there are no internal pull-downs on a pin when the MCU is powered down.

I would appreciate all help.

#gpio #io #stm32l4

[S.Ma]

Posted on February 04, 2018 at 07:39

My 2 cents: When the supply voltage is equal to its ground, you typically get in most electronic programmable components the ESD protection back to back diods or equivalent. If you want to confirm this, take any board, short VDD to GND and run a diod check with a multimeter.

For I2C dedicated pins or oscillator pins, the protection may be different behaviour which you can too check easily through spec and confirm with diod check (which is also sometime used to test soldering pin is ok). 

[Szymon PANECKI]

Posted on February 04, 2018 at 09:12

Hi Lukasz,

State of GPIOs for STM32L4 MCUs:

• under reset- high impedance
• just after start up (when the Power On Reset is released) - analog input
• in application - according to user configuration

Exceptions could be special functions pins: NRST pin , BOOT0 pin , Debug (JTAG, SWD) pins, oscillator pins. For example at least one of JTAG lines (PA15, which acts as JTDI) has a pull-up in reset state in order to activate debug session under reset.

Regards

Szymon

[Lukasz Przenioslo]

Posted on February 04, 2018 at 10:02

Hello Szymon,

Thank you for answer. I understand reset state is equal to powered down state.

[Szymon PANECKI]

Posted on February 04, 2018 at 10:21

You're welcome. Yes, I confirm: 

reset state = power down state.

Regards

Szymon

[waclawek.jan]

Posted on February 05, 2018 at 15:39

Szymon,

reset state = power down state

Lukasz asked for powered down state (VCC = VSS = 0 V).

In that case, KIC's answer from above applies.

JW

[Lukasz Przenioslo]

Posted on February 05, 2018 at 18:12

Do you guys mean this?

[waclawek.jan]

Posted on February 05, 2018 at 18:42

Yes.

The 5V-tolerant pins don't have the upper diode connected directly to VDD(IO) - there is some undisclosed protection circuitry though. Note the requirement for maximum Input voltage on FT_xxx pins in DS - it's something like 'the lowest of supply voltages plus some particular value (e.g. 4.0V for 'L476)'. That hints that the protection may be equivalent to a 4.0V Zener diode (in series with a reverse-polarized ideal diode).

Also note, that unless you provide external hard short (which would be very unusual), there's no guarantee for VDD=VSS just because you don't supply current explicitly through the VDD pins. Once you start to push current through the protection circuitry/diodes to VDD, that voltage may quite well rise up to the point where the mcu starts to work. As usually there's not enough current to support full-scale run of the mcu, depending on particular circumstances it may start some oscillations of sort.

JW

[Lukasz Przenioslo]

Posted on February 05, 2018 at 18:48

Thank you for answer,

Yes in fact I am not ground the VCC pin. I am only closing the P Fet providing positive voltage value. By saying that VCC = VSS, i meant with pulldowns.