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Lukasz Przenioslo
Lukasz Przenioslo
Associate III
February 3, 2018
Question

GPIO state at power down

  • February 3, 2018
  • 2 replies
  • 3129 views
Posted on February 03, 2018 at 23:40

Hello there,

According to the datasheet, the GPIO ports circuit diagram looks like this in STM323L4x2:

0690X00000609awQAA.png

From this diagram I understand that at powerdown (VCC = VSS = 0 V) the I/O pin state is high impedance. But is that 100% correct? I want to make sure before I make a design move that would save me some components. But for this I need to know either there are no internal pull-downs on a pin when the MCU is powered down.

I would appreciate all help.

#gpio #io #stm32l4
This topic has been closed for replies.

2 replies

S.Ma
S.Ma
Principal
February 4, 2018
Posted on February 04, 2018 at 07:39

My 2 cents: When the supply voltage is equal to its ground, you typically get in most electronic programmable components the ESD protection back to back diods or equivalent. If you want to confirm this, take any board, short VDD to GND and run a diod check with a multimeter.

For I2C dedicated pins or oscillator pins, the protection may be different behaviour which you can too check easily through spec and confirm with diod check (which is also sometime used to test soldering pin is ok). 

Szymon PANECKI
Szymon PANECKI
Senior III
February 4, 2018
Posted on February 04, 2018 at 09:12

Hi Lukasz,

State of GPIOs for STM32L4 MCUs:

  • under reset- high impedance
  • just after start up (when the Power On Reset is released) - analog input
  • in application - according to user configuration

Exceptions could be special functions pins: NRST pin , BOOT0 pin , Debug (JTAG, SWD) pins, oscillator pins. For example at least one of JTAG lines (PA15, which acts as JTDI) has a pull-up in reset state in order to activate debug session under reset.

Regards

Szymon
Lukasz Przenioslo
Lukasz PrzeniosloAuthor
Associate III
February 4, 2018
Posted on February 04, 2018 at 10:02

Hello Szymon,

Thank you for answer. I understand reset state is equal to powered down state.

Szymon PANECKI
Szymon PANECKI
Senior III
February 4, 2018
Posted on February 04, 2018 at 10:21

You're welcome. Yes, I confirm: 

reset state = power down state.

Regards

Szymon

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