Posted on September 13, 2017 at 15:55
Hello
We are using FMC for communication with FPGA. FPGA has memory-mapped periphery implemented in compatible mode for synchronous non/multiplexed PSRAM/NOR.
We are facing problem with misinterpreted spikes/cut pulses in CLK signal at higher frequencies (see pictures below).
These are screenshots of ILA blocks (logic analyzers in FPGA). It shows how bus is interpreted and seen by logic in FPGA.
detail...
It seems that these ''cut'' CLK pulses shows before NWE signal is toogled. Also this only happens when we write data...not when reading from memory.
It is can be fw/hw bug or it is a feature of MCU?
Used MCU: STM32F767ZI
FCLK 96MHz
FMC configuration
FMC CLK 6MHz (FMC div 16), continuous
Timing.AddressSetupTime = 15;
Timing.AddressHoldTime = 15; Timing.DataSetupTime = 255; Timing.BusTurnAroundDuration = 15; Timing.CLKDivision = 16; Timing.DataLatency = 2; Timing.AccessMode = FMC_ACCESS_MODE_A;Memory type PSRAM
Address 24bits
Data 16 bits
Clock Burst Read Write
Address valid signal enabled
NWAIT signal enabled
Regards,
Daniel
#psram #fmc #clock-spikes