I am attempting to temporarily disable Flash ECC interrupts, for the purpose of validating data stored on internal flash, and discovered that the ECC Interrupt Enable settings seem to have no effect.
I am using an STM32H743, and have used the code below to intentionally trigger ECC interrupts. I experience the same interrupt (HardFault_IRQ), with the same FLASHn_SR values when a byte with an ECC mismatch is read, whether or not FLASH_CR_SNECCERRIE and/or FLASH_CR_DBECCERRIE are set. I have verified the bit settings via ST-Link/V2 ISOL debugger both before and after the interrupt occurs, and I'm using STM32CubeIDE.
// CODE FOR INTENTIONALLY TRIGGERING ECC ERROR
char dummy[32];
char * pointer = (char*) FLASH_BANK2_BASE;
flash_eraseSector(FLASH_SECTOR_TOTAL);
memset(dummy,0xAF,sizeof(dummy));
HAL_FLASH_Program(FLASH_TYPEPROGRAM_FLASHWORD, FLASH_BANK2_BASE, (uint32_t)dummy);
dummy[0] = *pointer; // does not trigger ECC interrupt
memset(dummy,0x5A,sizeof(dummy));
HAL_FLASH_Program(FLASH_TYPEPROGRAM_FLASHWORD, FLASH_BANK2_BASE, (uint32_t)dummy);
dummy[0] = *pointer; // triggers ECC interrupt
Does anyone know anything about this? Is there another register than must be used?
