I have an application, which uses 2 channels of TIM1 to drive a full bridge d-class power stage in order to generate a sinusoidal signal. FSW is 200kHz. The CCR1 and CCR2 registers of TIM1 have to be updated at sampling frequency, so I am using TIM8 to trigger a DMA burst transfer into TIM1 registers. I could not get any otmer timer than TIM8 to work, which I assume is because of non-advanced timers being on different APB and different DMA controller.
Ideally, I would like to transfer a burst of 2 16-bit values on every DMA trigger and the source buffer would look like (CCR1_0, CCR2_0, CCR1_1, CCR2_1, CCR3_0... and so on) . DBL field in DCT register of TIM1 seem to allow burst length of 2. But The DMA controller can only be configured for bursts of 4 or 8 transfers. The only way I as able to make it work is to basically configure TIM1 for burst length of 4, which forces me to store values for channels 3 and 4 in the source buffer even though they are not used (so the array looks like (CCR1_0, CCR2_0, CCR3_0, CCR4_0, CCR1_1, CCR1_1... and so on). This means that I am effectively wasting half of the source buffer space because of the dummy CCR3 and CCR4 writes i have to perform. Since the source buffer stores about 10k samples, this means I am wasting about 40kB of RAM space on dummy data.
After the lengthy description of the problem: is there a way to achieve an effective burst length of 2?
The requirement is that CCR1 and CCR2 have to be updated within 1 TIM1 PWM cycle and there can be absolutely no CPU intervention. The reason behind this is that the power stage is rated at over 1.5kW RMS and any erratic behaviour or distortion generally has quite destructive consequences.
I thought about trying to disable burst in DMA controller, while leaving the burst mode on in TIM1, and then somehow producing 2 DMA triggers during single cycle of TIM8 in order to transfer 2 values to TIM1. Is the operation of burst mechanism in TIM1 somehow tied to the burst mode setting in the DMA engine, or will doing multiple separate DMA transfers still udate consequent registers in TIM1?
