In an application, for reasons I don't want to discuss here I try to write the program being binary fully compatible for both 'F407 and 'F427. Sticking to the 'F407 as subset, the 'F427 seems to be pretty compatible, the only exception I am aware so far being PWR_CR.VOS (which I simply leave at its reset value) and the VBAT/TEMP handling in ADC (and this is easy to work around).
Today I stumbled upon a more subtle difference, which doesn't appear to be documented properly. I have an external SRAM-like device connected through FSMC/FMC. I use Bank 1, mode A for both read and write (i.e. FSMC_BCR1.EXTMOD = 1, FSMC_BTR1.ACCMOD = 0b00, FSMC_BWTR1.ACCMOD = 0b00). I use a 16-bit databus (FSMC_BCR1.FSMC_BCR1=0b01). I use an asynchronous WAIT, (i.e have ASYNCWAIT set) but I don't think it's pertinent to this problem; in the case described below the nWAIT input was inactive.
I have set FSMC_BWTR1.BUSTURN=4. When I performed a 32-bit write, F(S)MC correctly split it into two 16-bit writes, but while in 'F407 it inserted between these writes a delay corresponding to FSMC_BWTR1.BUSTURN (I've tried several values), the 'F427 appeared to insert a fixed zero or one cycle delay (depending on what exactly is the definition of this delay), ignoring FSMC_BWTR1.BUSTURN setting.
In RM0090 rev.18, comparing the FSMC_BWTR1.BUSTURN description in FSMC and FMC chapters reveals, that both describe an identical set of exceptions, albeit in different wording (bonus question: why the different wording?). However, 'F407 appears to work differently, as the description mentions only one exception for back-to-back asynchronous writes:
No bus turnaround delay is inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed and D mode.
ST, please comment.
JW
