2020-11-12 01:40 AM
I wonder if there is some known issue?
With logic analyzer I confirmed that I had extra clock pulses in the SPI after the data was read.
The chip is STM32F427@180MHz.
PCLK2 is 90 MHz
SPI4 (master) is used with 16 bits and with prescaler 64, half duplex, single data line.
I'm reading two 16-bit words with HAL_SPI_Receive(), and after it returns, I turn NSS high.
What I saw with logic analyzer was that after NSS goes high, there were still 16 clock pulses coming out.
When I changed the prescaler even bigger (128), there were no more extra clock pulses.
The chip in the other end has 2 MHz maximum SPI clock.
More accurately:
2020-11-20 12:10 AM
HAL doesn't care. They just enable SPI, wait the specified numbers of frame and disable SPI. As HAL doesn't care to be precise, the disable comes too late, hardware already started to receive the next frame.
JW
2020-11-22 11:36 AM
One would think giving the count and using blocking transfer should do...