ETH: anybody used KSZ8863RLL?

[LCE]

Heyho,

until now I only used STM32 with the LAN8742, in a few weeks I'll get my 2nd custom board, but this time with the "dual" PHY KSZ8863RLL.

It's connected via RMII, for setup MDIO (and optionally I2C for the registers not accessible via MDIO).

Are there any known issues or "pitfalls" with this PHY?

Thanks in advance,
LCE

PS: interesting that there is no "ETH" label... :D

[LCE]

> a SAM would see the same as an STM

Yes, but... the STM has surely another register setup.

Edit:

@Andrew Neil so until now we spammed this thread with "ask Microchip yes / no", please let's keep it at that.

And I hope some STM32 + KSZ8863 user finds the way here and shares some experience.

[Pavel A.]

We've made few projects with similar Microchip switches (not exactly this). The SPI or I2C interface gives easy access to all registers, make sure to connect it. The MDIO interface is provided for compatibility and is limited.

Note also their offering on the website: "Microchip's complimentary and confidential MicroCHECK design review service, which offers insight from the initial concept to the final PCB layout, is available to customers who are using our products in their projects. You can confidently submit your design materials in a secure and private setting, and our expert engineers will provide individualized feedback to enhance your design. "

Difference from the simple LAN... PHY is basically that the MCU is permanently connected to port #3, always at 100 Mbit/s, full duplex. So you can throw away code for detection of cable connect/disconnect, speed and duplex. Also throw away the whole MDIO config. stuff, you'll use the full management interface over I2C or SPI instead. Interrupt is optional; usually you can just poll the registers every so often.

[LCE]

@Pavel A. Thanks for the input!

For now I actually want to start with the MDIO (before struggling with another I2C peripheral), as it looks most stuff is handled automatically by the KSZ8863.

Checking for link status:

From another of your posts I already learned that the RMII side is always "linked" at 100-FULL.

But I think I could use the standard BSR register which each of the 2 PHYs has, with the same Link Status bit as LAN8742.

If that doesn't work, I'll try the "Auto-Negotiation Link Partner Ability Register" (reg 5), if the PHY doesn't show 100-FULL ability, link's not up.

The interrupt is also connected, but for now no intention to use it.

The Microchip offer is quite nice, but schematics and PCB layout are (usually) no problem.
Compared to the STM32-eval boards my PCBs could win prizes... :grinning_face_with_sweat: (okay, that's unfair when it comes to Nucleo with its 100 options per pin)

[LCE]

Here's some good info, saves me from trying to play with opcode 00 :D

https://community.st.com/t5/stm32-mcus-embedded-software/stm32h743-with-cube-1-40-ethernet-mdio-usage-for-phy/td-p/322108

[LCE · Accepted solution]

I have my board with STM32H733, KSZ8863RLL, LAN9512 up and running.

Here's the most important advice:

a) use internal RMII clock

b) use I2C (or SPI) - which is a must for a)

MDIO only allows access to a few basic registers (as already mentioned by Pavel), but to enable internal RMII clock (recommended by datasheet), a register only accessible via I2C / SPI must be written. (Bad design IMO).

[JSpencer]

would you be willing to share the ethernet portion of your project? 

I would like to use the ksz8863rll with the STM32F107 IC in one of my projects but I'm not quite sure how to configure the ethernetif.c file produced by LWIP. Or are you using the mongoose library or something similar to work with this PHY?

[LCE]

Sorry, I am not allowed to share.

Oryx has a lot of useful stuff, it seems:

https://www.oryx-embedded.com/doc/ksz8863__driver_8c_source.html

[LCE]

... but I can tell you the steps I use for "bringing up" the KSZ:

1) hardware reset by MCU, pulling down KSZ's RSTN pin, then release it (this step is probably not required)

2) I2C: first communication "alive check": read the chip ID

3) I2C: set RMII clock to internal (bit 3 in reg 198d (?))

4) I2C: check LINK status (KSZ8863_PORT1_STAT0 and KSZ8863_PORT2_STAT0)

5) I2C: power down unused port

Have you checked all the "strap" pins with pull-resistors?

[JR5]

Hi,

Is this true?

"to enable internal RMII clock (recommended by datasheet), a register only accessible via I2C / SPI must be written."

If using Clock mode 3 the IC does not require any registers to be set and can be left as default, as per the figure below.

I'm only mentioning this as I have not exposed the I2C interface on my design which I've just received from manufacture...

Thanks,

Joe

[LCE]

> Is this true?

On my board, unfortunately yes.

> ... I have not exposed the I2C interface on my design which I've just received from manufacture...

Oh my... the good news is, that the KSZ uses the same pins for I2C as for MDIO.

Have you wired at least the external clock output back to the input? If yes, and if you have a serial resistor replace it with 0R.

Question to @JR5 : from which datasheet version is that "table 6-5" ?