EOT to early

[dbahr]

Hi.

implementing a SPI master (NOT using HAL) with software based SS i am searching for the right way to detect the end of a transmission to release the SS again.

EOT (in SPI_SR) gets set when the last Bit is is set to the MOSI Lane. 

--> so this is too early since the there is a full clock cycle remaining until SS should be reset.

Is there any Signal that could be used to know that the Transfer on the SPI BUS is full finished? Using the Hardwaree SS is working fine But since I have a multi-slave environment I would like to use software based SS.

[Issamos]

Hello @dbahr 

You can use th EOT and a clock cycle delay. EOT is set ->a clock cycle delay (using a TIM for example) ->release the SS again.

Best regards.

II

[dbahr]

thank you for your quick reply. Was hoping that there is a dedicated signal that could be used directly to know that transmission is finished. 

Best regards

David

[Issamos]

Your best option for this is the EOT signal.

When your question is answered close the topic by choosing a best answer.

Best regards.

II

[Pavel A.]

In full duplex (bi-directional) mode, you can use the RX non empty flag. It means that all master bits have been completely clocked out and slave bits clocked in. When it set, SS can be turned off.

[dbahr]

Hi, RX non empty Flag is also triggered too early. As I understand it is wordwise and not going 0 when the last bit is transmitted. 

[Issamos]

I think, in that case,my solution can give you exactly what you are looking for (signal EOT start TIMER and then the TIMER signal trigger the SS reset.

Best regards.

II

[waclawek.jan]

If you have control over slaves, try the other CPHA setting.

JW

[dbahr · Accepted solution]

my current workadound is to use EOT as a trigger to release the SS and restrict the minimum speed that can be used on SPI.

YELLOW: NSS

RED: SCLK

125kbit/s (NSS is released too early): 

1Mbit/s (NSS is released correctly):