Effect of pull up without supplying power to MCU

[cWagh.1]

As shown in above figure.

The EXT/GPIO pin directly connected to MCU with pull up resistor (10K).

So once the switch press the PMOSFET start switching supply to MCU.

Please let me know the effect of voltage on EXT/GPIO pin without suppling power to MCU.

[waclawek.jan]

Which STM32? Which pin?

Look at the type of given pin in the pins table in datasheet for your STM32.

TT pins have a protection diode to the chip's VDD pin, which at that moment is at the VSS (ground) potential, so current will flow through it. Calculate that current using Ohm's law and compare to maximum allowable given as "IO current injection" in the DS.

If it is a FT pin, no current is flowing and you must not exceed 4V above the chip's VDD (which at that moment is at VSS) on it.

JW

[cWagh.1]

Thanks for reply.

MCU-STM32L073CZT6 and Pin No 25-FT type. VDD-3.3V.

As the EXT/GPIO pin having voltage 3.3V continuously without supplying power(MCU_VDD) to MCU.Just I wanted to know, this may be lead to damage the pin of MCU or this may be causes any other effect on performance of MCU..?

[ONadr.1]

I solved a similar problem. Nothing will happen to the processor, but after disconnecting the VDD, current will flow continuously through the 10k resistor into pin protection diode. Current wil be cca (VDD-0.5)/10000 (in Amp). So, nothing for battery powered equipment.

[Peter BENSCH]

It would be questionable whether an interrupt can be detected anyway, since the STM32 only receives voltage at the time of the edge at the EXTI and arrives more or less delayed (depending on the clock source and init programme) in the main routine.

But probably you want to realise something like a latching by having the GPIO switch the FET active as soon as the STM32 is powered up, right?

In that case, probably the cleanest solution would be to disconnect the GPIO input from SW1/R6 and connect another n-channel FET (logic level) in between (gate to GPIO, drain to SW1, source to GND). The GPIO then remains active as long as the device is to operate and then switches itself off by deactivating the GPIO or the FETs.

A time delay between GPIO and gate is probably not necessary because the voltage at VDD is discharged much later than the GPIO has turned off the FET.

Good luck!

Regards

/Peter