DSB instruction for implementing delay after an RCC peripheral clock enabling

[dtom7]

Hi,

I'm new to STM32 microcontrollers, specifically STM32G070RB which is an Arm Cortex M0+ MCU.

From section 5.2.16 (page# 134) of https://www.st.com/resource/en/reference_manual/rm0454-stm32g0x0-advanced-armbased-32bit-mcus-stmicroelectronics.pdf

Peripheral clock enable registers

Caution: The enable bit has a synchronization mechanism to create a glitch-free clock for the peripheral. 
After the enable bit is set, there is a 2-clock-cycle delay before the clock be active, which the software must take into account.

As per https://www.st.com/resource/en/errata_sheet/dm00037591-stm32f405-407xx-and-stm32f415-417xx-device-limitations-stmicroelectronics.pdf Section 2.2.13 Delay after an RCC peripheral clock enabling, 3 workarounds are mentioned.

• Use the DSB instruction to stall the Arm® Cortex®-M4 CPU pipeline until the instruction has completed.
• Insert “n” NOPs between the RCC enable bit write and the peripheral register writes (n = 2 for AHB
peripherals, n = 1 + AHB/APB prescaler for APB peripherals).
• Simply insert a dummy read operation from the corresponding register just after enabling the peripheral
clock.

I hope these workarounds are applicable for STM32G070RB also.

I'm planning to use the DSB instruction after enabling the peripheral clock.

void enable_gpioa_clock(void)
{
    RCC_IOPENR |= (0x1U << 0x0U);
    __asm volatile("DSB"); 
}

Are there any drawbacks in using DSB instruction here?

Thanks in advance.

@Jan Waclawek 

[STOne-32]

Dear @dtom7 ,

Welcome in STCommunity . 

indeed in STM32G0 this is specified in our specification and require 2 AHB clock cycle before it will be taken into account .

my recommendation in general is just to read back the same register IOEPNR which is always valid on all cases and also if in future you would like to move to others Cores .

DSB will work as well in this case as It will take at least 1 AHB cycle  and next instruction in code will follow .

Hope it helps you 

Cheers,

STOne-32

[Tesla DeLorean]

Or just read-back the register to force the write-buffers to complete.

__DSB(); is the CMSIS definition

RCC_IOPENR |= (0x1U << 0x0U);

RCC_IOPENR;

[waclawek.jan]

> just to read back the same register IOEPNR which is always valid on all cases and also if in future you would like to move to others Cores .

Except where it isn't.

https://community.st.com/t5/stm32-mcus-products/erratum-quot-delay-after-an-rcc-peripheral-clock-enabling-quot/m-p/579949

JW

PS.

Cross post with relevant discussion at stackoverflow; my take in above thread and also here - in short, there's probably no universally good solution and I prefer setting clocks all at once at beginning of the program and then do something else useful until the peripherals are accessed.