That's a bit difficult: During erase or page programming, the external flash (the whole chip!) is not readable, it will only respond to status register reads (on some devices, it's possible to suspend the erase/program operation temporarily, but that's even more complicated). So, during these operations, the CPU can only execute from internal flash.
As the program/erase may take a long time, that might not be acceptable.
One partial solution would be to use two external flash chips, either with QSPI in dual flash mode (not possible due to pin availability on the L431RC) but only one active at any time by switching the FSEL bit, or two wired in parallel except for NCS. The L431RC offers two choices, PA02 and PB11, for QUAD_BK1_NCS, these could easily be switched dynamically. Or even some simple glue logic for selecting either of two. One chip for code, one for data, but this means that data access always has to be done from internal flash ...
If even that is not acceptable, the last resort would be two flash chips but with identical contents. While one is busy during erase/programming, the other is used for code execution. After completion of flash operation switch the roles and repeat the operation on the other chip.
