Does anyone know how to find out the Core revision number?

[anonymous.8]

Posted on March 12, 2017 at 17:12

Hi. I have an STM32F746 Discovery board purchased late last year from Digi-Key. It uses a STM32F746NG chip. I have not found any documentation anywhere that defines which revision of the Cortex M-7 core it uses. I am programing using FreeRTOS and its portability layer has a port.c function for the CM-7 core revision r0p1. I see the latest (but still dated 2015) ARMCortex-M7 Processor Technical Reference Manual  is Revision r1p0 which presumably is later than revision r0p1.

How do I find out what revision the core is in any particular STM ARM chip?

Thanks.

[Tesla DeLorean]

Posted on March 12, 2017 at 20:58

I have a decoder for this and the FPU variant, but not near the system it is on

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0489d/Cihhbddh.html

 

SCB->CPUID  <- check this register

DBGMCU->IDCODE

  

https://community.st.com/0D50X00009XkaRrSAJ

 

[Tesla DeLorean]

Posted on March 12, 2017 at 20:59

Check SCB->CPUID

printf('r%dp%d\n', ((SCB->CPUID >> 20) & 0x0F), (SCB->CPUID & 0x0F));

[anonymous.8]

Posted on March 13, 2017 at 00:04

Clive, thanks for the info. on the SCB->CPUID register. It is documented, as I found out, in the PM0253 Cortex-M7 Programming  manual. By the time I read your second post here I had already written a routine to recover the rnpn number.

And I discovered that it is r0p1 for the STM32F746NG chip as used in the STM746 Discovery kit. One of the links you gave above mentioned they thought that STM had only licensed the r0p1 core from ARM.

Thanks to all who have posted.

[Tesla DeLorean]

Posted on March 13, 2017 at 00:30

One of the threads went through a couple of edits, but the NUCLEO-F767 had the r1p0 part, the FPU-D and 2MB of FLASH

The FPU-S devices probably just going to be the r0p1 core, unless ST steps the part, and that would reflect in the errata documentation.

[Imen.D · Accepted solution]

Posted on March 13, 2017 at 11:29

Hi,

As mentioned by Clive One, you may find more details in the

http://www.st.com/content/ccc/resource/technical/document/errata_sheet/4d/39/a6/8c/84/47/47/67/DM00145382.pdf/files/DM00145382.pdf/jcr:content/translations/en.DM00145382.pdf

 :

[Tesla DeLorean]

Posted on March 13, 2017 at 15:43

Ok, but what are the plans moving forward? Is the core going to be updated in future releases of the F74xxx and F75xxx products?

[Tesla DeLorean]

Posted on March 13, 2017 at 15:47

Stuff with code tends to get locked in moderation for a while. These are the routines I built to do quick diagnostic checks

//****************************************************************************
 
void CORECheck(void) // sourcer32@gmail.com
{
  uint32_t cpuid = SCB->CPUID;
  uint32_t var, pat;
 
  printf("CPUID %08X DEVID %03X REVID %04X\n", cpuid, DBGMCU->IDCODE & 0xFFF, (DBGMCU->IDCODE >> 16) & 0xFFFF);
 
  pat = (cpuid & 0x0000000F);
  var = (cpuid & 0x00F00000) >> 20;
 
  if ((cpuid & 0xFF000000) == 0x41000000) // ARM
  {
    switch((cpuid & 0x0000FFF0) >> 4)
    {
      case 0xC20 : printf("Cortex M0 r%dp%d\n", var, pat); break;
      case 0xC60 : printf("Cortex M0+ r%dp%d\n", var, pat); break;
      case 0xC21 : printf("Cortex M1 r%dp%d\n", var, pat); break;
      case 0xC23 : printf("Cortex M3 r%dp%d\n", var, pat); break;
      case 0xC24 : printf("Cortex M4 r%dp%d\n", var, pat); break;
      case 0xC27 : printf("Cortex M7 r%dp%d\n", var, pat); break;
 
      default : printf("Unknown CORE\n");
    }
  }
  else
    printf("Unknown CORE IMPLEMENTER\n");
}
 
//****************************************************************************
 
// FPU Programmer Model
// http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0489b/Chdhfiah.html
 
void FPUCheck(void) // sourcer32@gmail.com
{
  uint32_t mvfr0;
 
  printf("%08X %08X %08X\n%08X %08X %08X\n",
    *(volatile uint32_t *)0xE000EF34,   // FPCCR  0xC0000000
    *(volatile uint32_t *)0xE000EF38,   // FPCAR
    *(volatile uint32_t *)0xE000EF3C,   // FPDSCR
    *(volatile uint32_t *)0xE000EF40,   // MVFR0  0x10110021 vs 0x10110221
    *(volatile uint32_t *)0xE000EF44,   // MVFR1  0x11000011 vs 0x12000011
    *(volatile uint32_t *)0xE000EF48);  // MVFR2  0x00000040
 
  mvfr0 = *(volatile uint32_t *)0xE000EF40;
 
  switch(mvfr0)
  {
    case 0x00000000 : puts("No FPU"); break;
    case 0x10110021 : puts("FPU-S Single-precision only"); break;
    case 0x10110221 : puts("FPU-D Single-precision and Double-precision"); break;
    default : puts("Unknown FPU");
  }
}
 
//****************************************************************************

Edited 5-Dec-2018, the forum transition totally snarled up the code formatting, reposting with clean/current code.

[Imen.D]

Posted on March 14, 2017 at 10:23

Hi Clive,

There is no plan for new device revision for F74xxx and F75xxx products.

So, there is no plan to embed a new core revision.

Thanks

Imen

[Tesla DeLorean]

Posted on February 15, 2018 at 19:55

The H743ZI has the Cortex-M7 r1p1 core

CPUID 411FC271 DEVID 450

Cortex M7 r1p1

STM32H7xx

C0000018 2000B328 00000000

10110221 12000011 00000040FPU-D Single-precision and Double-precision