cancel
Showing results for 
Search instead for 
Did you mean: 

DMA triggered DMA

richard239955
Associate II
Posted on March 05, 2014 at 11:32

Hey everybody,

Is it somehow possible to start/enable/trigger a DMA transfer with the help of another DMA transfer? I'm thinking of the following scenario:

- DMA transfer 1 is timer triggered (every 1us) and transfers memory data to a GPIO data register, therefore creating a 1MHz bit pattern on the output pins (20 consecutive transfers)

- DMA transfer 2 is also timer triggered (every 1ms) and should retrigger DMA transfer 1, in order to repeat that bit pattern with a frequency of 1kHz.

What I know from the reference manual is that you should not configure a DMA stream while it is enabled. But I'm thinking of using DMA transfer 2 to write the SxNDTR (number of data) register of DMA transfer 1. Would this lead to any complications?

(btw: I know I could replace DMA transfer 2 by an interrupt.)

Thanks in advance for any replies,

Richard

#stm32f4 #dma #timer
2 REPLIES 2
Posted on March 05, 2014 at 12:04

You should really start doing something like this with thorough reading the fine manual.

> What I know from the reference manual is that you should not configure a DMA stream while it is enabled.

It's not that you shouldn't - you can't.

But it's kind of moot, since when NDTR reaches zero, the stream disables itself, so you would need to reenable it by writing one to DMA_SxCR.EN. But prior to that, you need to clear the respective flags in DMA_LISR/DMA_HISR by writing to DMA_LIFCR/DMA_HIFCR; but these are not located consecutively (except for Stream0), so you can't do that in one DMA. And all other registers for a stream lie beyond DMA_SxCR, so they can't be written in one DMA either.

I would do something different. As you need some trigger for the memory-to-GPIO transfer anyway (for which you need DMA2, see other recent DMA-to-GPIO threads), you will probably use a timer for that, setting it to output a pulse at the 1MHz pace. Now you can chain that timer with another one, which would gate it so that you achieve the required bursts of DMA-to-GPIO transfers.

Not trivial at all, but IMO doable.

JW

richard239955
Associate II
Posted on March 05, 2014 at 14:01

Using two chained timers could do the trick, thanks.