2011-09-01 08:14 AM
I'm noticing a strange issue when I enable a DMA stream to SPI where the NDTR register changes from my value to 0xFFFF.
Below is a code snippet for the DMA transfer function://Setup DMA for TX
DMA2_S3PAR = 0x4001300C; DMA2_S3M0AR = (uint32)&tx_pkt->preamble; DMA2_S3NDTR = tx_pkt->length + CC1120_TX_PKT_OVERHEAD; //Enable DMA stream DMA2_S3CR_bit.EN = 0; while( DMA2_S3CR_bit.EN != 0 ); DMA2_S3CR_bit.EN = 1; SPI1_CR2_bit.TXDMAEN = 1;***As soon as I execute this the NDTR register changes to 0xFFFF
I have confirmed that the NDTR register for the stream is correctly loaded with my length value, but when I enable TXDMA in the SPI peripheral for some reason the NDTR register is set to 0xFFFF. The DMA stream does work, and I can see the correct SPI TX data, but since the NDTR is changed to 0xFFFF the length of the stream is incorrect.Has anyone seen this behavior before?Also for reference below is my DMA stream init routine:void stm32_dma2_ch3_init( void )
{ //SPI1 TX - DMA2 Stream3 Channel3 DMA2_S3CR_bit.EN = 0; while( DMA2_S3CR_bit.EN != 0 ); //Enable DMA2 clock RCC_AHB1ENR_bit.DMA2EN = 1; //DMA Channel3 DMA2_S3CR_bit.CHSEL = 3; //Highest Priority DMA2_S3CR_bit.PL = 3; //Memory and Peripheral Data Size 8-bit DMA2_S3CR_bit.MSIZE = 0; DMA2_S3CR_bit.PSIZE = 0; //Memory increment mode + 1 DMA2_S3CR_bit.MINC = 1; //Peripheral increment mode fixed DMA2_S3CR_bit.PINC = 0; //Data transfer direction, Memory to Peripheral DMA2_S3CR_bit.DIR = 1; //Peripheral Flow Control - The peripheral is the flow controller DMA2_S3CR_bit.PFCTRL = 1; //Transfer Complete Interrupt Enable DMA2_S3CR_bit.TCIE = 1; //Enable DMA2 interrupts ( NVIC_DMA2_CH3 = 59 ) SETENA1_bit.SETENA59 = 1;} #spi #dma2011-09-01 10:26 AM
Might be because you've set the peripheral as the flow controller.
2011-09-01 10:33 AM
Is that incorrect? In this setup the SPI is a slave, so I figured since the clock source for the SPI is external I would need the SPI peripheral to be the flow controller.