differences between STM32H7 rev V and rev Y

[Mr_M_from_G]

Hello,

we use STM32H7 in our new development. I was excited about the announcement of the new revision V because it promises an increase of speed from 400MHz to 480 MHz. My distributor told me that except for that, the devices were hard- and software compatible.

Now I set a rev V STM32H742 into our prototype and after hours found out that there are a number of differences in ADC alone.

• So my first general question is, if there is a paper summarizing all the differences?
• My second question is, if the new ADC will in any case have at least the same performance as the old one (we use it at the edge of the old specs)?
• The third question is, when will a new package for CubeMX be available that support the new revision? I have STM32H7 package ver 1.2.0 and it complains when I try to set sysclk to 480 MHz.

Now some questions in detail:

• There is a new clk divider by two for adc_ker_clk. With the old settings for rev Y I get only half the samples per second. Can I simply double pll2_p_ck to get back to the old samples per second or are there limits in the ADC peripheral. (I tried it and it works but I need to be sure, that it is within specs)
• Datasheet of rev V gives for 14 bits resolution only 3.3 MSps which is too little for us. But it also says that this is with SMP = 2.5 while it is also possible to set SMP = 1.5, which is the value used in rev Y specs for all resolutions. Is there something wrong with using SMP = 1.5 with 14 bit resolution (or any other resolution) for rev V ?
• Is it still true, that fast channels are channels 0 .. 5 (RM0433 Rev 6 page 910)? Datasheet of STM32H742 says: (page 283) "4. Fast channels correspond to PC0, PC1, PC2, PC3, PA0, and PA1". We use PA6/7 = ADC1 INx3 and PC4/5 = ADC2 INx4 which would be fast for RM0433 but not for the datasheet.

I think we really need solutions for that because we can't stick to rev Y, it will not be produced anymore I guess (??)

So any help especially from ST members is greatly welcome

Thanks a lot

Martin

[Rob vdH]

Hi,

I'm having the same problem. Needed a high sample rate/precision ADC. To my surprise I only got half of the expected sample rate. I could not figure out what was wrong until I saw that strange /2 clock divider in the reference manual.

For my project I minimally need an ADC doing 4 Msps/12 bit. For this I need to set fADC at 64 MHz (2*32) which CubeMX doesn't like (it automatically selects an ADC prescale factor of 2). I can override this in my code but I hesitate. I do not know what the maximum safe (not /2 divided) clock frequency of the ADC is. Can anyone shed some light on this?

Kind regards,

Rob.

[flyer31]

We use STM32H7 ADC with Y and V in somehow "compatible mode". As far as I remember, the main thing is that we HAVE to use the BOOST mode, then it worked with both versions nicely with identical settings (but no high-speed requirements in our application, and without "stupid CubeMX / HAL", just pure register programming).

[Rob vdH]

Investigated the strange /2 ADC clock divider a bit further and inside the ADC_ConfigureBoostMode function I came across the following code:

else /* STM32H7 silicon Rev.V */
  {
    freq /= 2U; /* divider by 2 for Rev.V */
 
    if (freq <= 6250000UL)
    {
      MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL);
    }
    else if (freq <= 12500000UL)
    {
      MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0);
    }
    else if (freq <= 25000000UL)
    {
      MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1);
    }
    else /* if(freq > 25000000UL) */
    {
      MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0);
    }

The /2 prescaled frequency seems to have the same range as Rev Y. So, I think it's safe to simply double fADC to get the correct sample rate. CubeMX does not know this, and sets the wrong ADC clock prescale every time I use it :-(.

I think the /2 divider was not added to limit the ADC sample rate, they probably needed a clock signal with double the frequency inside the ADC circuit.