We are using the STM32f413 with the DFSDM unit for converting the PDM stream generated from the external ADC. The clock is generated externally. We are using the OSR of 512 and sinc3 filter with an integration time of 8, a regular channel with continuous DMA conversion and fast mode enabled. We found out that delay in callback HAL_DFSDM_FilterRegConvCpltCallback is generated of around 90us. In the reference manual RM430 there is no specification about any latency from DFSDM unit. However, we found some specification in application note AN4990 that the latency introduced is
Tlatency = Tsampling * [(FOSR*FORD) + (FORD+1)]. We have changed the FOSR to half of its original value and the latency was about half shorter (in our case around 90us and in the second case with a shorter filter around 45us)
1. Is the latency same for regular and fast mode, since the data rate is different. Can we get the exact equation? According to our measurements, it looks it should be a little shorter latency. Can you please update the reference manual.
2. According to this latency, does it mean the first ~FOSR*FORD cycles or samples are discarded, and therefore the data count starts after FOSR*FORD samples ?
Thank you
Andrej Campa
