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Delay from CKT_EN to CK_CNT

KSun.11
Associate II

In the RM0008, Figure 120 on page 379, it says "as soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock, CK_INT. " as shown below. However in the figure, the CK_CNT appears 2 cycles after the CEN bit became 1. Given the prescale ratio of 1, I wonder how to explain that there are 2 cycles before the CK_CNT follows the response.

Why two cycles?0693W000000UOJlQAO.png

3 REPLIES 3

IIRC this or similar question has been discussed here maybe last year, and even answered by ST insider. Try searching the forum.

JW

Sorry, I am new to this forum. And I did search when key in my subject title, but maybe I searched for the wrong keywords.

Oh, I found one posted six months ago.

https://community.st.com/s/question/0D50X0000BFzSF7SQN/how-timers-in-stm32f7-start-workig

It is exactly I am asking... but I still don't get the conclusion. So it is manual errors? How can I teach this to my students...