I am using the NUCLEO-U575ZI-Q.
I am using the OSPI peripheral in QSPI mode.
The device I am communicating with needs a longer delay after the CS line is asserted low.
I have tried setting the "ChipSelectHighTime" to 8, but I think this only affects the "number of clocks which the chip select must remain high between commands." I do not believe this controls the timing of a delay after the CS is asserted.
I also looked into the "Delay Block"; however, this looks like it controls delays for reads only if I understand it correctly.
