Delay Chip select line STM32U5 OSPI

[LCorb.2]

I am using the NUCLEO-U575ZI-Q.

I am using the OSPI peripheral in QSPI mode.

The device I am communicating with needs a longer delay after the CS line is asserted low.

I have tried setting the "ChipSelectHighTime" to 8, but I think this only affects the "number of clocks which the chip select must remain high between commands." I do not believe this controls the timing of a delay after the CS is asserted. 

I also looked into the "Delay Block"; however, this looks like it controls delays for reads only if I understand it correctly. 

[Tesla DeLorean]

How long of a delay?

Could you drive the pin as a GPIO manually around HAL_OSPI interactions?

[KDJEM.1]

Hello @LCorb.2,

Could you please check the refresh rate and the chip select boundary.

Refresh rate (REFRESH) required for PSRAMs memories. The chip select must go high each (REFRESH x OCTOSPI clock cycles), configured depending on the memory datasheet.

Chip select boundary (CSBOUND) configured depending on the memory datasheet. The chip select must go high when crossing the page boundary (2^CSBOUND bytes defines the page size).

For more information about the configuration of OCTOSPI parameters, I recommend you to look at AN5050 Table 8. STM32CubeMX - Configuration of OCTOSPI parameters.

Thank you.

Kaouthar

[LCorb.2]

I am not running a PSRAM, I was hoping for a delay after the CS went low to add extra time before the clock and data are transmitted.  THE CSBOUND would be a different functionality.

[LCorb.2]

Yes, this works, but I need this all automated with DMA for performance.  AAdding a manual GPIO toggle is quite a long delay; I was looking for a few extra clock cycles worth of delay.