Debugging dual core Bootloader on STM32H7

[banelapel]

I'm trying to develop a bootloader for a dual core STM32H7, running on the CM7.

I'm starting by trying to modify my user project for it.

I've moved the user code up a bank:

FLASH   (rx)   : ORIGIN = 0x08020000, LENGTH = 896K

and put in a IVT offset on line 118 of system_stm32h7xx_dualcore_boot_cm4_cm7.c

#define VECT_TAB_OFFSET         0x00020000U

I have the debugger set up per ST's video, the CM7 connects under reset, halts all cores, and downloads both the CM4 and CM7.

However, since I've made those two modifications, the CM4 starts up with the CM7, and I can't connect to the CM4 debugging session.

With the offset and flash origin reverted to normal, the project debugs as expected: I run debug on the CM7, and it waits at 

while (__HAL_RCC_GET_FLAG(RCC_FLAG_D2CKRDY) != RESET)

for me to start the CM4 debugging session, then goes forward.

The CM7 project otherwise runs, interrupts seem to be working properly, so it seems the table is finding itself in the right place.

How do I properly set up the project for debugging the user code?

[Tesla DeLorean]

Does the M4's IVT need to move? Isn't that typically off at 0x08100000 ? Or at the very least unrelated to the one for the M7

Might I suggest using a linker symbol to set the address for SCB>VTOR, and not compile time defines which are prone to error or misinterpretation.

[banelapel]

I intend to leave the CM4 right where it is at 0x08100000. No changes there.

[banelapel]

(nevermind this)