I'm using the same board, works like a charm, memory-mapped mode.
Make sure that it's not running at more than 100 MHz.
Here's my almost non-HAL setup:
OSPI_HandleTypeDef hOspi1;
OSPI_HandleTypeDef hOspi2;
/* OCTOSPI2 basic init function */
/* input clock is 1/2 HCLK */
uint8_t OctoSpi2_Init(void)
{
uint8_t u8RetVal = 0;
/* Initialize OctoSPI ----------------------------------------------------- */
hOspi2.Instance = OCTOSPI2;
/* clock & GPIO initialization */
HAL_OSPI_MspInit(&hOspi2);
/* start OFF */
OCTOSPI2->CR = 0;
/* device config registers
* DCR1 .. DCR4
*/
/* DCR1:
* MTYP = 100 Hyperbus memory mode
* DEVSIZE
* CHST
* DLYBYP = 0 delay block is used
* FRCK = 0 no free running clock
* CKMODE = 0 clock low when idle
*/
OCTOSPI2->DCR1 = OCTOSPI_DCR1_MTYP_2 |
((OSPI_HYPERRAM_SIZE - 1) << OCTOSPI_DCR1_DEVSIZE_Pos) |
((OSPI_HYPERRAM_NCS_HITIME - 1) << OCTOSPI_DCR1_CSHT_Pos);
/* DCR2:
* WRAPSIZE = 0 wrapped read OFF
* PRESCALER = 1 divide by 2 -> 100 MHz = max at 3.3V
*/
OCTOSPI2->DCR2 = (OSPI_HYPERRAM_WRAP_ZERO << OCTOSPI_DCR2_WRAPSIZE_Pos) |
((OSPI_HYPERRAM_CLK_DIV - 1) << OCTOSPI_DCR2_PRESCALER_Pos);
/* DCR3:
* CSBOUND = 23 set to 2^n memory size
* MAXTRAN = 0 unused
*/
OCTOSPI2->DCR3 = (OSPI_HYPERRAM_CSBOUND << OCTOSPI_DCR3_CSBOUND_Pos);
/* DCR4:
* REFRESH = 500 NCS must be released, even for PSRAM for internal refresh
*/
OCTOSPI2->DCR4 = OSPI_HYPERRAM_REFRESH;
/* CR: control register
* no polling
* no interrupts
* FMODE = 0 indirect mode, set to memory-mapped mode later
* FTTHRES = 4 FIFO threshold
* FSEL = 0 nc in octal mode
* TCEN = 0 no timeout counter
* DMAEN = 0 no DMA
* ABORT = 0 no ABORT request
* EN = 0 ENable set later
*/
OCTOSPI2->CR = ((OSPI_HYPERRAM_FTHRES - 1) << OCTOSPI_CR_FTHRES_Pos);
/* TCR: timing config
* SSHIFT = 0 no read sample shifting
* DHQC = 1 delay hold quarter cycle ON
* DCYC = 0 dummy cycles between readd addr & data
*/
OCTOSPI2->TCR = OCTOSPI_TCR_DHQC |
(OSPI_HYPERRAM_DCYC << OCTOSPI_TCR_DCYC_Pos);
/* Hyperbus configuration
* memory-mapped mode configuration
* CR, DCR1, CCR, WCCR, DLR, AR
*/
/* HLCR: HyperBus latency configuration register
* TRWR[7:0] = x read write recovery time
* TACC[7:0] = y yccess time
* WZL = 0 latency on write access
* LM = 1 fixed latency
*/
OCTOSPI2->HLCR = (OSPI_HYPERRAM_RW_REC_TIME << OCTOSPI_HLCR_TRWR_Pos) |
(OSPI_HYPERRAM_LATENCY << OCTOSPI_HLCR_TACC_Pos) |
OCTOSPI_HLCR_LM;
/* CR: clear FMODE -> exit MM for now */
OCTOSPI2->CR &= ~OCTOSPI_CR_FMODE;
/* DCR1: Hyperbus from register access to memory */
OCTOSPI2->DCR1 &= ~OCTOSPI_DCR1_MTYP_0;
/* CCR & WCCR:
* DQS signal enabled (used as RWDS)
* DTR mode enabled on address and data
* address and data on 8 lines
*/
/* READ: CCR */
OCTOSPI2->CCR = OCTOSPI_CCR_DQSE |
OCTOSPI_CCR_DDTR | OCTOSPI_CCR_DMODE_2 |
OCTOSPI_CCR_ADSIZE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADMODE_2;
/* WRITE: WCCR */
OCTOSPI2->WCCR = OCTOSPI_CCR_DQSE |
OCTOSPI_WCCR_DDTR | OCTOSPI_WCCR_DMODE_2 |
OCTOSPI_WCCR_ADSIZE | OCTOSPI_WCCR_ADDTR | OCTOSPI_WCCR_ADMODE_2;
/* DLR: data length = 1 byte */
OCTOSPI2->DLR = 0;
/* AR: address reset */
OCTOSPI2->AR = 0;
/* update state */
hOspi2.State = HAL_OSPI_STATE_CMD_CFG;
/* LPTR: lo-power timeout reset */
OCTOSPI2->LPTR = 0;
/* HW IO MUX setup */
/* MUX OCTOSPIM->PCR[n] */
OCTOSPI2->CR &= ~OCTOSPI_CR_EN;
/* NO multiplexed mode */
OCTOSPIM->CR = 0;
/* PORT 2:
* select signals & enable
* hi port 2 4..7
* lo port 2 0..3
* NCS 2
* DQS 2
* clock 2
*/
OCTOSPIM->PCR[1] = ( OCTOSPIM_PCR_IOHSRC_1 | OCTOSPIM_PCR_IOHSRC_0 | OCTOSPIM_PCR_IOHEN |
OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOLEN |
OCTOSPIM_PCR_NCSSRC | OCTOSPIM_PCR_NCSEN |
OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_DQSEN |
OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_CLKEN );
/* DELAY block */
/* disable the output clock and enable the access to the phase selection SEL[3:0] */
DLYB_OCTOSPI2->CR = DLYB_CR_SEN;
/* set delay */
DLYB_OCTOSPI2->CFGR = 0 & DLYB_CFGR_SEL_Msk;
/* disable the access to the phase selection, enable output */
DLYB_OCTOSPI2->CR = DLYB_CR_DEN;
/* enable in peripheral -> clear bypass */
OCTOSPI2->DCR1 &= ~OCTOSPI_DCR1_DLYBYP;
/* clear all status flags */
OCTOSPI2->FCR = 0xFFFFFFFF;
/* CR: memory-mapped, no timeout */
OCTOSPI2->CR &= ~OCTOSPI_CR_TCEN;
OCTOSPI2->CR |= OCTOSPI_CR_FMODE;
/* CR: enable peripheral */
OCTOSPI2->CR |= OCTOSPI_CR_EN;
/* set state (for DMA & HAL stuff) */
hOspi2.State = HAL_OSPI_STATE_BUSY_MEM_MAPPED;
return u8RetVal;
}
/* basic GPIO & DMA init */
void HAL_OSPI_MspInit(OSPI_HandleTypeDef *phOspi)
{
GPIO_InitTypeDef GPIO_InitStruct = { 0 };
if( phOspi->Instance == OCTOSPI2 )
{
/* OCTOSPI2 clock enable */
__HAL_RCC_OCTOSPIM_CLK_ENABLE();
__HAL_RCC_OSPI2_CLK_ENABLE();
/* reset */
__HAL_RCC_OSPI2_FORCE_RESET();
__HAL_RCC_OSPI2_RELEASE_RESET();
__HAL_RCC_GPIOG_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
/**OCTOSPI2 GPIO Configuration
PF0 ------> OCTOSPIM_P2_IO0
PF1 ------> OCTOSPIM_P2_IO1
PF2 ------> OCTOSPIM_P2_IO2
PF3 ------> OCTOSPIM_P2_IO3
PF4 ------> OCTOSPIM_P2_CLK
PF12 ------> OCTOSPIM_P2_DQS
PG0 ------> OCTOSPIM_P2_IO4
PG1 ------> OCTOSPIM_P2_IO5
PG10 ------> OCTOSPIM_P2_IO6
PG11 ------> OCTOSPIM_P2_IO7
PG12 ------> OCTOSPIM_P2_NCS
*/
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Pin = OCSPI2_IO1_Pin | OCSPI2_IO0_Pin |
OCSPI2_IO2_Pin | OCSPI2_CLK_Pin |
OCSPI2_IO3_Pin | OCSPI2_DQS_Pin;
GPIO_InitStruct.Alternate = GPIO_AF9_OCTOSPIM_P2;
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
GPIO_InitStruct.Pin = OCSPI2_IO7_Pin | OCSPI2_IO5_Pin | OCSPI2_IO4_Pin;
GPIO_InitStruct.Alternate = GPIO_AF9_OCTOSPIM_P2;
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
GPIO_InitStruct.Pin = OCSPI2_IO6_Pin | OCSPI2_NCS_Pin;
GPIO_InitStruct.Alternate = GPIO_AF3_OCTOSPIM_P2;
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
}
}
