2024-06-06 07:10 AM
Hi,
I have the following configuration:
1. ADC converts values and writes it to memory with DMA
2. DAC outputs the ADC data also with a DMA
3. Both, the ADC and the DAC are triggered by HRTIM TimerA at a rate of 700kHz
All works fine, I can see the data coming out on DAC.
In my program I need to change the period value of Timer A occasionally. If I do the first write to Timer A
period register, the DAC stops with a underrun error. I have figured out that it doesn`t matter which HRTIM
register I write to, if a write happens it ends up in underrun error of DAC. There is no DMA tranfer error only the underrun error. In HRTIM configuration I have enabled preload and I use HAL_HRTIM_UpdateEnable() and HAL_HRTIM_UpdateDisable() before doing a write acces to the registers, but it's still not the solutions and the program ends up in DAC underrun error.
Additional observation is - the underrun error is not triggered by the first write access to the HRTIM resgisters, there are multiple writes (approx. 3-10) bevor it ends up in DAC underrun error, but it definitely always trigger this error when I write to HRTIM registers, if not, everything works just fine.
I run out of ides what could be the reason, but it must have to do with the write acces generating a trigger, and DAC is inside an write cycle,...
Waht I have tried so far:
1. Cheking the DAC ready flag befor writing to HARTIM registers
while(!(DAC1->SR & DAC_SR_DAC1RDY));// || !(DAC1->SR & DAC_SR_DAC2RDY));
while(!(DAC2->SR & DAC_SR_DAC1RDY));
2. Disable DAC, write to HRTIM, enable DAC
3. Disable DMA writing to HRTIM enable DMA
HAL_ADC_Stop_DMA(&hadc1);
HAL_ADC_Stop_DMA(&hadc2);
HAL_DAC_Stop_DMA(&hdac1, DAC_CHANNEL_1);
HAL_DAC_Stop_DMA(&hdac2, DAC_CHANNEL_1);
...
Nothing seems to prevent the DAC underrun, if anyone has any idea where else I could
check - would be so great!
Thanks and regards,
Benedikt
2024-08-02 01:57 AM
Hello Benedikt,
What may be missing in the information you gave above is the system clock frequency to programmed. The DAC underrun may be caused by the priority conflict between cpu access to hrtim (requiring code execution and ram access) and then DMA access to DAC, requiring also ram access. So, this may lead to an impact on dma latency and then dac underrun.
It may be interesting to use different sram between dma and cpu in this case, to avoid latency increase.
Please have a look on system architecture chapter for additional explanation.
Best regards.