DAC kernel clock and CPU clock domains: how to configure them to work asynchronously?

[jeremierafin]

Hi,

My problem: how to configure DAC so that CPU core clock and DAC kernel clock can be asynchronous (i.e: 250MHz and 70MHz)?

Details:
- my hardware is based on the STM32H523CET6
- configuration:
  - SYSCLK (HCLK) running at 250MHz (with PLL1 from HSE=TCXO @26MHz)
  - TIM7 generates a 48kHz rectangle signal
  - DAC1 is triggered by TIM7 trgo
  - PLL2 configured for PLL2R=70MHz
- code loop:
  - pulling on TIM7 SR's UIF bit (update interrupt flag) until it is set
  - clear UIF bit
  - toggling DAC out between 0 and 0xFFF0 values
  - loop again (infinitly)
- results:
  - when DAC is clocked by HCLK (ADC,DAC Clock Mux = HCLK): OK :)
  => output is toggling with a rectangle frequency of 24kHz (as expected)
  - when DAC is clocked by PLL2 (ADC,DAC Clock Mux = PLL2R): KO :(
  => output is randomly toggling

My feeling is that the transfert of the DAC out value (DHR12L1 register) does not work if clocks (CPU and DAC ones) are asynchronous. Can you help me?

(Note: I need to run the ADC with an accurate frequency, so I need to set the mux to PLL2R. And I need DAC and ADC to work at same time. So far, the DAC does not satisfy me as its out is randomly generating the signal I program...)

Thanks!

P.S.: for any detail, I attache the Cube project "Hello" in the two above configurations (ok.tar.xz and ko.tar.xz). But feel free to ask me any detail!

[TDK]

> output is randomly toggling

Can you show this? Just a bit of jitter?

A better solution would be to handle this in DMA. Transfer to the DAC register when TRGO happens.

[jeremierafin]

On the oscilloscope:

- when it is OK: perfect rectangle signal, freq is 24kHz

- when it is KO: the rectangle high or low levels last between 1 and about 20 time the expected duration; average freq is about 5kHz

Not simple to give you a picture of the oscilloscope (too old to export screenshots). But trust me: this is not "a bit of jitter", unless 2000% would be "a bit " for you! :D

Regarding the DMA, of course, in my full application, I use it. But I have exactly the same behavior: with DMA or CPU managed. As I preferred to provide a simpler example, I gave this code snippet without DMA.

Once again: my feeling is that when the DAC register is changed, by the CPU directly, or by the DMA, since the bus master clock differs from the slave one, then a clock domain synchronization would be required. Does my feeling make sense? Do I miss a configuration to get this synchronization?

Note that I did not find anything in the errata list...