DAC kernel clock and CPU clock domains: how to configure them to work asynchronously?

[jeremierafin]

Hi,

My problem: how to configure DAC so that CPU core clock and DAC kernel clock can be asynchronous (i.e: 250MHz and 70MHz)?

Details:
- my hardware is based on the STM32H523CET6
- configuration:
  - SYSCLK (HCLK) running at 250MHz (with PLL1 from HSE=TCXO @26MHz)
  - TIM7 generates a 48kHz rectangle signal
  - DAC1 is triggered by TIM7 trgo
  - PLL2 configured for PLL2R=70MHz
- code loop:
  - pulling on TIM7 SR's UIF bit (update interrupt flag) until it is set
  - clear UIF bit
  - toggling DAC out between 0 and 0xFFF0 values
  - loop again (infinitly)
- results:
  - when DAC is clocked by HCLK (ADC,DAC Clock Mux = HCLK): OK :)
  => output is toggling with a rectangle frequency of 24kHz (as expected)
  - when DAC is clocked by PLL2 (ADC,DAC Clock Mux = PLL2R): KO :(
  => output is randomly toggling

My feeling is that the transfert of the DAC out value (DHR12L1 register) does not work if clocks (CPU and DAC ones) are asynchronous. Can you help me?

(Note: I need to run the ADC with an accurate frequency, so I need to set the mux to PLL2R. And I need DAC and ADC to work at same time. So far, the DAC does not satisfy me as its out is randomly generating the signal I program...)

Thanks!

P.S.: for any detail, I attache the Cube project "Hello" in the two above configurations (ok.tar.xz and ko.tar.xz). But feel free to ask me any detail!

[STea]

Hello @jeremierafin ,

First of all, I wanted to thank you for your detailed explanation and outstanding detailing of this issue.

after examination of the code and after double-checking the tests that you did i share your assumption about this being a silicon bug most probably related to the STM32H562xx/563xx/573xx device errata - Errata sheet

I submitted a ticket (ticket number 200203 for internal reference only) to confirm this erratum is valid for H523 series as well and will keep you updated.
Regards