About jeremierafin

jeremierafin · 2025-01-08

*** Sorry I closed my previous post (https://community.st.com/t5/stm32-mcus-products/dac-kernel-clock-and-cpu-clock-domains-how-to-configure-them-to/m-p/759757#M270108) by mistake. This one reopens it. ***Hi,My problem: how to configure DAC so that C...

jeremierafin · 2025-01-08

Hi,My problem: how to configure DAC so that CPU core clock and DAC kernel clock can be asynchronous (i.e: 250MHz and 70MHz)?Details:- my hardware is based on the STM32H523CET6- configuration: - SYSCLK (HCLK) running at 250MHz (with PLL1 from HSE=TCX...

jeremierafin · 2025-01-09

Attached file corresponds to when CPU is stopped before the infinite loop (so after all inits).

jeremierafin · 2025-01-09

I tried these configuration for Prescaler/Period:- 2604 / 1 (initial)- 2604 / 2- 2604 / 3- 2605 / 1- 2605 / 2- 2605 / 3- 2606 / 1- 2606 / 2- 2606 / 3- 10000 / 100- 1000 / 1- 100 / 1The "signature" of the "randomness" is changed, but the problem remai...

jeremierafin · 2025-01-08

On the oscilloscope:- when it is OK: perfect rectangle signal, freq is 24kHz- when it is KO: the rectangle high or low levels last between 1 and about 20 time the expected duration; average freq is about 5kHzNot simple to give you a picture of the os...

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Are DAC kernel clock and CPU clock domains correctly synchronized?

DAC kernel clock and CPU clock domains: how to configure them to work asynchronously?

Re: Are DAC kernel clock and CPU clock domains correctly synchronized?

Re: Are DAC kernel clock and CPU clock domains correctly synchronized?

Re: DAC kernel clock and CPU clock domains: how to configure them to work asynchronously?