2017-03-20 05:59 AM
There appears to be conflicting information in the maximum APB1/APB2 speed on the STM32F411 chip, in both the data sheet and the STM32CUBEMX software. I was hoping someone here may know more about why this is.
In the manual (RM0383), in one place it quite clearly states
The maximum frequency of the AHB domain is 100 MHz. The maximum allowed frequency of the high-speed APB2 domain is 100 MHz. The maximum allowed frequency of the low-speed APB1 domain is 50 MHz.
Then, later on during the register section (RCC->PPRE2), it states
The software has to set these bits correctly not to exceed 84 MHz on this domain.
Similarly, for the low speed APB2 domain, it states:
The software has to set these bits correctly not to exceed 42 MHz on this domain.
Well, which is it? Can I set these to 100/50 MHz or only a max of 84/42 MHz? Anecdotally, I can say that setting them to 100 MHz has not caused me issues so far.
I wouldn't have even noticed it except that in the STM32CUBEMX software, it gives an error if I try to set the APB1 clock above 42 MHz. Interestingly, no such error is given if I set APB2 above 84 MHz.
Anyone have more info on this? There's nothing in the errata list about it. The data sheet is still in its initial version.
Maybe the original intent of the chip was to be run at 84 MHz and they simply didn't update it everywhere?
2017-03-20 06:28 AM
Sounds like a software bug.
2017-03-20 07:32 AM
Sounds like a software bug.
What? The mistake in the RM? ;)
JW
2017-03-20 08:34 AM
'
STM32CUBEMX software, it gives an error if I try to set the APB1 clock above 42 MHz
'I've used the 100/50 setting for APB2/APB1, and honestly don't think the 50/25 setting would make any sense. That it says 84/42 in the manual is just lack of editing for the F411 context.
2017-03-20 08:46 AM
So, it isn't documentation first anymore?
Shall we consider Cube/MX or any other 'library' or software piece as the normative reference?
Am I too naive to consider the wording in RM as an order of magnitude more serious problem than any Cube/MX bug?
JW
PS. Checked DS which is 100/50 too.
2017-03-20 09:06 AM
The 100/50 is specified in the Reference Manual under the Clock Tree Diagram. It used to be marked on the APB2/APB1 clock branches, but that seems to have been dropped. It is a useful cross check for the APB and TIMCLK
'Several prescalers are used to configure the AHB frequency, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB domain is 100 MHz. The maximum allowed frequency of the high-speed APB2 domain is 100 MHz. The maximum allowed frequency of the low-speed APB1 domain is 50 MHz'
The I2C and USART make reference to 42 MHz
I find the editing of the manual to be sloppy, the CubeMX reinforces the lack in communication between the units. That the APB is limited to 84/42 on a 100 MHz part is the least rational outcome, who'd do that? I can't imagine a Validation Engineer signing off on that kind of non-sense.
Who thought having a dozen mutations of the F4 was a good plan? 84, 100, 168, 180 MHz?
2017-03-20 09:51 AM
??
So, it isn't documentation first anymore?
Not sure I'm making that judgement, but I think documentation requires interpretation when logically/internal inconsistencies seem to stem from porting the existing boiler-plate text from prior parts.
I'm more inclined to go with the 'preponderance of the evidence' rather than 'beyond a reasonable doubt'
2017-05-03 02:47 AM
Hello,
Maximum APB1 and APB2 frequencies are the ones specified in the datasheet (documentation remains the first reference):
However, we still have the error reported in OP in the reference manual. This will be taken into consideration to be fixed in coming version of RM0383. For sure we should have all our resources aligned to avoid any confusion. Thanks for your help to achieve this.
Please note that there is no more problem with CubeMX to set a frequency > 42 MHz for APB1 (I am using the last version 4.20.1):
-Amel
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