Clock Frequency of L452RE

Chaitanya96 · ‎2024-01-29

Hello, I am having a confusion in understanding the Clock Frequencies for STM32L452RE. In the Datasheet its mentioned that "Several prescalers permit to configure the AHB frequency, the high speed APB (APB2) and
the low speed APB (APB1) domains" It also says "The maximum frequency of the AHB and the APB
domains is 80 MHz" which is correct. But if you see on the Block Diagram both APB1 and APB2 Share the same clock i.e 80MHz . How would we justify if APB1 is Low Speed and APB2 is High Speed. It would be great to understand what its actually trying to say. Thanks in advance. Attaching the Images for Reference.

FBL · ‎2024-01-30

Hello @Chaitanya96,

First, you can refer to the reference manual section 2.2.2 Memory map and register boundary addresses: APB1 and APB2 are not the same bus/ clock.

The terms HS and LS are used to differentiate between the two APB domains, which can run at different clock speeds depending on the system configuration. The actual clock frequencies of APB1 (low speed) and APB2 (high speed) are determined by the prescaler/ divider values set in the RCC (Reset and Clock Control) registers. If both APB1 and APB2 are set to run at 80 MHz, they will indeed share the same clock frequency. However, the system can be configured such that APB1 runs at a lower frequency than APB2, hence the terms 'low speed' and 'high speed'.

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FBL · ‎2024-01-30

Hello @Chaitanya96,

First, you can refer to the reference manual section 2.2.2 Memory map and register boundary addresses: APB1 and APB2 are not the same bus/ clock.

The terms HS and LS are used to differentiate between the two APB domains, which can run at different clock speeds depending on the system configuration. The actual clock frequencies of APB1 (low speed) and APB2 (high speed) are determined by the prescaler/ divider values set in the RCC (Reset and Clock Control) registers. If both APB1 and APB2 are set to run at 80 MHz, they will indeed share the same clock frequency. However, the system can be configured such that APB1 runs at a lower frequency than APB2, hence the terms 'low speed' and 'high speed'.

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

I'm out of offce with limited access to my emails.
Happy New Year!

Chaitanya96 · ‎2024-01-30

Hi, @FBL,

Thanks for the reply. After carefully visiting the reference manual, in the RCC_CFGR I found the mentioned High Speed and Low Speed APB. Thanks again.

Andrew Neil · ‎2024-01-30

Also look at the graphical representation in the STM32CubeIDE Device Configuration Tool - it shows you all the clock sources, routing, etc.

This is a different chip, but shows the idea:

Chaitanya96 · ‎2024-01-30

Hello @Andrew Neil,

I have been currently working with HAL and since in L452RE clock configuration, both APB1 and APB2 both have same maximum clocks similar to the example you stated, it created the confusion. But after referring reference manual my doubt was cleared for this particular controller. Thanks