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Clarification about timing inconsistencies on G473CETx LQFP48

etheory
Senior II

Hi there!

I am working on a project using an STM32G473CETx LQFP48 MCU in STM32CubeIDE.

I am using TIM2 to simultaneously:

1.) Generate a PWM output signal using:

  • Channel 1 - PWM Generation CH1 - Combined PWM1 mode
  • Channel 2 - PWM Generation No Output - Combined PWM 2 mode

2.) Proving a DAC sync using the

  • Timer 2 Trigger Out event

3.) Provide a ADC sync using the

  • Timer 2 Trigger Out event

4.) Provide a GPIO DMA stream event using

  • TIM2_UP

I am initializing everything in this sequence:

 

HAL_DAC_Start_DMA(&hdac1, DAC_CHANNEL_1, (const uint32_t*)dac_data, 16, DAC_ALIGN_12B_R);

HAL_ADC_Start_DMA(&hadc1, (uint32_t*)adc_data, 8*128);

HAL_DMA_Start(&hdma_tim2_up, (uint32_t)mp_gpio_data, (uint32_t)&GPIOC->BSRR, 8);

__HAL_TIM_ENABLE_DMA(&htim2, TIM_DMA_UPDATE);

HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1);

 

My expectation of this would be that everything starts synchronously in lock step, but instead, what I get is the following:

1.) The TIM2 PWM outputs 1 PWM cycle first

2.) Then the GPIO outputs 1 output

3.) Then the DAC starts


This is weird, as they should all start synchronously at exactly the same time.

What is going on here?

And don't tell me it's HAL. I know HAL sucks, but here it's working just fine.

It sets the TIM start bit which is what it should do, and they should all start running at the same time but they don't.

TIM2 settings:

etheory_1-1729422205478.png

etheory_2-1729422234024.png

etheory_0-1729422188102.png

DAC settings:

etheory_4-1729422288820.png

etheory_3-1729422268922.png

DMA Settings:

etheory_5-1729422331911.png

 

Also, where in the docs (RM0440) can I find what the timing specifics of the TIM2_UP DMA signal are? There are timing diagrams for Timer 2 Trigger Out Event (listed as Update Event (UEV) but no equivalent for TIMx_UP:

etheory_6-1729422488984.png

Thanks!

1 REPLY 1
etheory
Senior II

OK Based on this diagram:

etheory_0-1729423023625.png

I get why I get one PWM pulse before the first other signal, since a UEV is not generated when the timer first starts.

So that makes sense. i.e. it has to go through a full counter cycle (causing one PWM output) before it resets for the first time to generate the first update event, which is then when the first DMA .

But that still doesn't explain why TRGO and TIMx_UP signals don't fire simultaneously, which makes the GPIO output and DAC outputs different, with the DAC lagging by 1 Update event.