Choosing package for STM32H743 SPI HS - BGA or LQFP ?

[cipek]

Hi,

I'm interfacing external ADC - 16 bit, 10MSPS (AD7626) with this microcontroller. STM32 SPI will work in slave mode, ADC will provide 80MHz clock. It will work in a burst mode - sampling 288 measurements x 16 bits at 5MHz.

I can't decide whether I need BGA for this or LQFP will be sufficient. I remember having issues with internal ADC under performing when used in LQFP package. I don't want to go with BGA unless I have to.

Cheers

[MasterT]

Check DS, H7 can get 133 MHz at max, no way to 250-300.

[cipek]

Could you elaborate on the speed please? Where did you get 133 MHz? I'm not familiar with DS, what is it?

[MasterT]

DS = data sheet.

https://www.st.com/resource/en/datasheet/stm32h743vi.pdf 

Table 106. SPI dynamic characteristics(1)   page 192.

[cipek]

I haven't looked into that table, thanks. In the clock configuration I can set the SPI clock to almost 200 MHz. I was hoping that this would be enough for 80 MHz signal. At this point I don't see any other options other than FPGA. 

[MasterT]

I can't find any stm32 uCPU with serial LVDS interface supported. STM32CubeMX lists some STM32MP2xx where :

 LTDC provide pixels to the LVDS display interface (LVDS).

specifically  for LCD/TFT display, not serial data like SPI

[AScha.3]

Hi,

the 80M SPI clock should be no big problem , but the AD7626 has LVDS interface : STM32 dont have this on SPI.

So you need LVDS -> cmos transceiver or a chip with native LVDS , typical a FPGA  with LVDS here is suitable.

[cipek]

So is 80 MHz an issue here or not? I was going to use a LVDC receiver like ADN4662. I've seen completely different opinions on this subject. 

[AScha.3]

If 80M SPI clock is the maximum you want, it should be no problem , with lvds receiver, short tracks, and damping resistors in all lines, maybe 33r .

I never tried this, my max SPI clock was 36 MHz, just for fun, to a TFT; using thin wires, free air, about 60mm long; was working fine, but more than double the given speed of the TFT, so reduced clock later, to avoid killing the TFT by overclocking.

[MasterT]

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@cipek wrote:

So is 80 MHz an issue here or not? I was going to use a LVDC receiver like ADN4662. I've seen completely different opinions on this subject. 

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Better to ask on analog.com, I have hard time to comprehend theirs DS.

First read confuses me on :

CNV to Last CLK (LSB) Delay 72 ns max (page 6 adc DS), having 18 clk gives 4 ns and consequently 250 MHz minimum.

Than small print note 2 indicates that:

(tCYC − tMSB + tCLKL)/n

and page 3 points 0.1 msps minimum sampling rate, so clk may be as low as 0.1x18  = 1.8 MHz

Regarding H7 SPI I have tested up to 83 MHz, reading data out af ad7983 /84. Not LVDS, regular CMOS 3.3V

10 cm dupont cables, series resistance 470 Ohm