2020-12-08 12:26 AM
Hello,
I was following a course and the section I'm at is using the ADC. They said the sampling time is 10us, but I calculated it to be around 2.3us.
Taken from the datasheet:
13.5 Channel-wise programmable sampling time
The ADC samples the input voltage for a number of ADCCLK cycles that can be modified
using the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can
be sampled with a different sampling time.
The total conversion time is calculated as follows:
Tconv = Sampling time + 12 cycles
Example:
With ADCCLK = 30 MHz and sampling time = 3 cycles:
Tconv = 3 + 12 = 15 cycles = 0.5 μs with APB2 at 60 MHz
So if the sampling time is set to 84, Tconv = 84 +12 cycles = 96. The ADCCLK with prescaler defaulted to 2 (check the ADC common control register (ADC_CCR) register), this means the ADCCLK = APB2 (84Mhz)/2 = 42MHz.
Now using the formals with Tconv = 96 and ADCCLK = 42MHz:
1/42MHz * 96 = 2.285714285714286e-6 or around 2.3us
Can you clarify this?
2020-12-08 06:41 AM
Okay, and what's the problem? Where's the mismatch? Where is the calculation which arrived at 10us?
JW
2020-12-08 07:04 AM
Well the course lecturer actually didn't show any calculations, which is why I derived my own and wanted to see if it's correct.
However, if I was to take a guess at how they got 10us, it would be the APB2 clock is 84MHZ and they set the sampling time to 84.
1/84MHz * 84 you get 0.000001s or 1us. This is how far I've got with trying to work out how they got 10us.
So my question is, is my calculations (shown in original post) correct for working out the sampling time when:
2020-12-08 09:02 PM
Their response to the calculations was:
hi, the default frequency of the core is 16MHz, hence the frequency for the adc is 8MHz (fclk/2) and when selecting number of conversion.
redo the calculation for 8MHz.
With that how they got around 10us, would be 1/8MHz * 84 = 10.5us
However now i'm confused as looking through the datasheets, taken from the reference manual (RM0090):
13.3.2 ADC clock
The ADC features two clock schemes:
• Clock for the analog circuitry: ADCCLK, common to all ADCs
This clock is generated from the APB2 clock divided by a programmable prescaler that allows the ADC to work at fPCLK2/2, /4, /6 or /8. Refer to the datasheets for the maximum value of ADCCLK.
It says that the ADCCLK is generated from the APB2 clock (84MHz) with the given prescaler.
Looking at the datasheet of the chip under 5.3 operating conditions it says the fpclk2 is 84MHz (max).
So is the fpclk 16MHz, as that's the size of the crystal used, or is it 84MHz as it mentions in the datasheets?