Can't dynamically change OC2REF for master and slave implementation

[Jtron.11]

Hi all, 

I am using STM32F7439Zi MCU, I would like to create the master + slave pwm signals with the relation that at the falling edge of the master, the slave's pulse will be started.  Both PWM signals has the same frequency, the duty cycle of the master and the slave can vary.

The set up as follow

TIMER 2 is set to Master:
Slave Mode: Disable
Channel1: PWM Generation CH1
Channel2: Output Compare No Output
Trigger Output (TRGO) Parameters:
- Trigger Event Selection: Output Compare (OC2REF)
Output Compare No Output Channel2:
- Mode: Active Level on match

TIMER 3 is set to Slave:
Salve Mode: Trigger Mode
Trigger Source: ITR1
Channel1: PWM Generation CH1
Channel2, 3, 4: Disabled

The code is simple:

HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1); // 1st output signal
HAL_TIM_OC_Start(&htim2, TIM_CHANNEL_2); // delay for the second signal to start
HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_1); // 2nd output signal

Straight from .IOC modify, I am able to create any duration of the master duty cycle as I want, but I can't modify the delay for the second PWM to start.

If I do:

__HAL_TIM_SET_COMPARE(&htim2, TIM_CHANNEL_1, new_duty_cycle); __HAL_TIM_SET_COMPARE(&htim2, TIM_CHANNEL_2, new_duty_cycle);

only the master PWM is updated and the new duty cycle is showing.  The slave PWM is staying the same.

For example, if I hardcode in the set up .ioc file for master = PWM mode 1, Pulse = 251, ARR = (5040-1), for 16.6KHz frequency, with 84MHz clock, and the OC2REF with Pulse Active Level on Match, Pulse = 252.  I will get both PWMs at 5%, 16.66KHz.

However, when I sent in the command to update the PWM duty cycle to 10%, my master PWM will be updated, but the slave PWM is staying at 5% of the master timing.  Seems like the OC2REF trigger didn't get update correctly.

Please give me some pointer to where can I trouble shooting this matter.

[Sarra.S]

Hello @Jtron.11, 

Could you check this example from the STM32CubeF7: STM32CubeF7/Projects/STM32F769I_EVAL/Examples/TIM/TIM_Synchronization/

[waclawek.jan]

Trigger mode of Slave-mode controller (as set in TIMx_SMCR.SMS) works in that way that upon arrival of TRGI sets TIMx_CR1.CEN. If TIMx_CR1.CEN is already set, any subsequent trigger is simply ignored.

It means, that if you want to apply the "shift" from the master, you have to clear TIMx_CR1.CEN somehow. One way to achiev it is to use One-Pulse mode in slave timer (i.e. TIMx_CR1.OPM = 1), where TIMx_CR1.CEN is cleared by hardware upon Update (i.e. after each period of timer). In other words, you want the slave timer to generate only one pulse per trigger, and then trigger it repeatedly from the master timer.

A different method might be to leave the slave timer running freely (i.e. not use the one-pulse mode) and use the Reset mode in the slave-mode controller of the slave timer.

JW