STM32H745 PTP Offloading

[JDWBE]

Hello

I’m busy with the implementation of PTP support inside my project.

I choose the STM32H745, because there is PTP support in hardware, with a nice offload function. After reading and try to understand the manual I create this code:

uint32_t SubSecondValue = 43;
			#define ADJ_FREQ_BASE_ADDEND      0x35455A81
			// Mask the Timestamp Trigger interrupt by clearing bit 12 of Interrupt enable register (ETH_MACIER).
			heth->Instance->MACIER &= ~(ETH_MACIER_TSIE);
			// Set bit 0 of Timestamp control Register (ETH_MACTSCR) to enable timestamping.
			//heth->Instance->MACTSCR |= 1;			// Done at the END! :)
			//Program Subsecond increment register (ETH_MACSSIR) based on the PTP clock frequency.
			heth->Instance->MACSSIR = (SubSecondValue<<16);

			// if you use the Fine Correction method, program Timestamp addend register (ETH_MACTSAR) and set bit 5 of Timestamp control Register (ETH_MACTSCR)
			heth->Instance->MACTSAR = ADJ_FREQ_BASE_ADDEND;
			heth->Instance->MACTSCR |= ETH_MACTSCR_TSADDREG;

			/* Poll the Time stamp control register until bit 5 is cleared. */
			while(ETH_GetPTPFlagStatus(heth, ETH_PTP_FLAG_TSARU) == SET);

			/* Enable the PTP Fine Update method Fine*/
			heth->Instance->MACTSCR |= ETH_MACTSCR_TSCFUPDT;

			/* Program the Time stamp high update and Time stamp low update registers
			* with the appropriate time value. */
			/* Set the PTP Time Update High Register */
			heth->Instance->MACSTSUR = 0;

			/* Set the PTP Time Update Low Register with sign */
			heth->Instance->MACSTNUR = ETH_PTP_PositiveTime | 0;

			/* Set Time stamp control register bit 2 (Time stamp init). */
			heth->Instance->MACTSCR |= ETH_MACTSCR_TSINIT;

			/* Set PPS frequency to 128 Hz */
			heth->Instance->MACPPSCR = 7;

			// Source: RM0399 Page 3039
			// 1. Program SNAPTYPSEL, TSMSTRENA and TSEVNTENA fields of Timestamp control Register (ETH_MACTSCR) to 0, 0, and 1 respectively.
			heth->Instance->MACTSCR &= ~((0b00)<<16); 	// Clear SNAPTYPSEL
			heth->Instance->MACTSCR &= ~((0b0)<<15); 	// Clear TSMSTRENA
			heth->Instance->MACTSCR |= (1 << 14);			// Set TSEVNTENA
			// 2. Program the PTOEN bit and DN field of PTP Offload control register (ETH_MACPOCR) to enable PTP Offload feature and domain Number to match with ingress PTP Sync message and send in egress PTP Delay_Req message.
			heth->Instance->MACPOCR &= ~((0b00000000)<<8); // Set Domain number to 0

			heth->Instance->MACPOCR |= 4; // Set APDREQEN
			// 3. Program the 80-bit Source Port Identity in PTP Source Port Identity 0 Register (ETH_MACSPI0R), PTP Source port identity 1 register (ETH_MACSPI1R) and PTP Source port identity 2 register (ETH_MACSPI2R) to match with ingress PTP Sync message and send in egress PTP Delay_Req message.
			heth->Instance->MACSPI0R = 0x57ffec79;
			heth->Instance->MACSPI1R = 0xfe81d0c8;
			heth->Instance->MACSPI2R = 0x0001;
			// 4. Program the DRSYNCR field in Log message interval register (ETH_MACLMIR) to indicate one PTP Delay_Req message is generated in response to how many received PTP Sync messages.
			heth->Instance->MACLMIR |= (2<<24);
			heth->Instance->MACPOCR |= 1; // Set PTOEN

This code is called just before “low_level_init” returns.

What I try to do: I want to implement PTP Slave device that reacts on PTP message and try to synchronize the time inside the hardware counter. Without any software interaction, hardware offload.  

When I sniff with Wireshark nothing happens, there is no communication send from the STM to the PTP master. What do I wrong?

My PTP master, is a off the shelve box specially made for PTP. The SYNC and Follow up data packets are sending though the network.

My ClockIdentity: 0xd0c857fffe81ec79

SourcePortID: 0x0001