Can Someone Prrovide me a SSD1963 Based Sample Project using GPIO Interface on a Neucleo-401RE Board

[Caan]

Posted on February 19, 2017 at 17:57

Can Someone Prrovide me a SSD1963 Based Sample Project using  GPIO Interface on a Neucleo-401RE Board.

[Imen.D]

Posted on February 23, 2017 at 17:37

Hi,

You can have a look at the Eval examples using FSMC with stm32CubeF4, it maybe helpful for you.

Also, you may find help on some threads in the STM32 forum where users share their projects

 as

 

https://community.st.com/0D50X00009XkeahSAB

 

Imen

[Caan]

Posted on February 24, 2017 at 06:58

I think STM32F401RE Doesn't have  FSMC Support So I am Looking forward for SSD1963 Communicating with STM32F401RE through GPIO(PARALLEL MODE) .

[chernobay]

Posted on February 25, 2017 at 03:20

https://arm-stm.blogspot.com/2016/12/ssd1963-init-collection.html

 

[chernobay]

Posted on February 25, 2017 at 03:21

https://github.com/golf2109/STM32F429ZI_SSD1963_FT5336

 

[Caan]

Posted on February 27, 2017 at 12:50

I have Attached the project file ,And This Code Seems to be non working.Kindly Help Me out.

________________ Attachments : stm32-ssd1963-master.rar : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006Hys8&d=%2Fa%2F0X0000000bDP%2FXb4oRxoWe5odI26WQpYa_OtRRcLKOP9F5cFR17FLiKc&asPdf=false

[AvaTar]

Posted on February 27, 2017 at 14:47

And This Code Seems to be non working.Kindly Help Me out.

What is not working ?

Have you verified the electrical connections ?

And each signal ?

And the signal sequence according to the SSD1963 datasheet ?

And the LCD init sequence and timing according to the datasheet ?

Don't expect someone else to get it working for you. It fails already because of missing hardware (Nucleo + LCD).

[Caan]

Posted on March 01, 2017 at 12:30

DATA PINS CONNECTED TO GPIOC (IN 16Bit Mode)

Control pins are Connected at PORTB

//0WR-1RD-2CS-4DC-5RST

#define Set_nWr GPIO_SetBits(GPIOB,GPIO_Pin_0); #define Clr_nWr GPIO_ResetBits(GPIOB,GPIO_Pin_0);

#define Set_nRd GPIO_SetBits(GPIOB,GPIO_Pin_1);

#define Clr_nRd GPIO_ResetBits(GPIOB,GPIO_Pin_1);

#define Set_Cs GPIO_SetBits(GPIOB,GPIO_Pin_2);

#define Clr_Cs GPIO_ResetBits(GPIOB,GPIO_Pin_2);

#define Set_Dc GPIO_SetBits(GPIOB,GPIO_Pin_4);

#define Clr_Dc GPIO_ResetBits(GPIOB,GPIO_Pin_4);

#define Set_Rst GPIO_SetBits(GPIOB,GPIO_Pin_5);

#define Clr_Rst GPIO_ResetBits(GPIOB,GPIO_Pin_5); #define LCD_WriteCommand(cmd) {Set_nRd;Set_Dc;Clr_nWr;Clr_Cs; GPIOC->ODR=((GPIOC->ODR&0x00ff)|(cmd<<8)); GPIOC->ODR=((GPIOC->ODR&0xff00)|(cmd>>8));delay_us(1); Set_nWr;Set_Cs;};

#define LCD_WriteData(data) {Set_nRd;Set_Dc;Clr_nWr;Clr_Cs; GPIOC->ODR=((GPIOC->ODR&0x00ff)|(data<<8)); GPIOC->ODR=((GPIOC->ODR&0xff00)|(data>>8)); delay_us(1); Set_nWr; Set_Cs;};

________________ Attachments : WP_20170301_001.jpg : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006Hyr1&d=%2Fa%2F0X0000000bDF%2FdNllUsKqh3XKW8OySDYhoo4HtPxe9_bE2k9UwRNdP1U&asPdf=falseWP_20170301_002.jpg : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HyrZ&d=%2Fa%2F0X0000000bDG%2FOJFZR8IoAqnE8ov7k6ed2_b.zGXKUIwITZmY.wQg850&asPdf=false

[AvaTar]

Posted on March 01, 2017 at 14:57

This is just some code, but no indication WHAT is not working. I'm currently not in the mood to decode direct-register-access code.

But getting an arbitrary MCU board + LCD display combination running requires to take a voltmeter or logic analyzer in hand, and verify each signal. Especially on the display end.

Without proper hardware/connections, it is never running.

No one here can do that for you.

And once you verified each signal individually, verify the proper sequence, according to the datasheet and bus mode.

I've been through this, too.

[markus239955_stm1_stmicro_com]

Posted on March 02, 2017 at 13:10

The timings in the ssd1963 project do not match to the datasheet of the vendor of your display.

http://techtoys.com.hk/Displays/TY500TFT800480/TY500TFT800480Rev01.pdf

this should be fixed first.