Why there is difference in detection logic? What is lowest pulse or transient dip the voltage detection logic will detect?
Is there any filtering in the PVD detection circuit internal to MCU? Is it same with BOR detection circuit?
What is the timing, or a transient response to which BOR & PVD will be immune to..?
@Fred and @Jocelyn RICARD Can you please forward this query to the Expert in this Voltage Monitoring ??
@Community member Can you able to help here ??
I tried going through manuals, but still not clear on difference of the above two behavior ??
Not really my area of interest
At some point you run out of electrons. Perhaps ensure the entire supply doesn't collapse faster than you can detect it and react to it.
Perhaps work with the local FAE responsible for your account, to understand the nuances of the implementation. Perhaps post as an Online Support Request
PVD would likely want different criterion so you can react in time.
The reset mechanisms want to ensure the synchronous logic doesn't get into indeterminate states, as this is a form of attack, beyond ensuring correct operation.