Bit definition for FLASH_ACR register seems to be wrong

[srikanth977]

Hello everyone,

I have been trying to program STM32F106C6T6 using CMSIS.

I came accross FLASH LATENCY programming where i have to configure 2 wait states in FLASH_ACR register.

As per Reference Manual, RM0008, I am seeing that value 2 will be used to configure 2 wait states, but CMSIS bit definition for FLASH_ACR register seems to be configuring value 4.

I am not sure if CMSIS is valid or if I am missing some basic concepts.

Attached are snaps of reference manual & CMSIS bit definition snap.

[waclawek.jan]

For most of non-single-bit fields in the registers, the CMSIS-mandated device headers for STM32 don't have actual *values* defined (rarely they have, but then they have it already shifted which is incorrect thing to do, but that's for a longer discussion ST does not want to participate in).

So, for example, FLASH_ACR_LATENCY_1 does not mean "one wait state", it merely means "bit nr. 1 in the LATENCY field". Dumb, I know, but that's how it is.

What I do, when I use these fields, is then this:

FLASH->ACR = 0

| (2 << FLASH_ACR_LATENCY_Pos) // set LATENCY to 2 waitstates

| (1 * FLASH_ACR_PRFTBE) // enable prefetch buffer

;

I also tend to define the missing constants myself, trying to follow this naming convention:

#define FLASH_ACR_LATENCY__2WS 2 // 2 waitstates

JW

JW

JW

[Piranha]

I would write the same code like this:

FLASH->ACR = 0
	| _VAL2FLD(FLASH_ACR_LATENCY, 2) // set LATENCY to 2 waitstates
	| FLASH_ACR_PRFTBE // enable prefetch buffer
;

Otherwise I do absolutely agree that those separate one-bit defines for multiple-bit fields are totally useless and that special named values must be defined non-shifted.