void ADC_Init(void) {
/*******************Horloges**************************/
SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN_Msk); //SYSCFG clock
delay(1000);
SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN_Msk); //RTCAPB clock
delay(1000);
SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN_Msk); //ADC12 clocks
delay(1000);
CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_PA0SO_Msk | SYSCFG_PMCR_PC3SO_Msk);
delay(1000);//PA0_C in analog mode
/********************ADC voltage regulator***************/
CLEAR_BIT(ADC1->CR, ADC_CR_DEEPPWD_Msk); //END DEEPPWD
SET_BIT(ADC1->CR, ADC_CR_ADVREGEN_Msk); //ENABLE ADC VOLTAGE REG
delay(1000);//WAIT VOLTAGE REG
/********************ADC calibration*********************/
CLEAR_BIT(ADC1->CR, ADC_CR_ADCALDIF_Msk);
SET_BIT(ADC1->CR, ADC_CR_ADCALLIN_Msk);
SET_BIT(ADC1->CR, ADC_CR_ADCAL_Msk);
while (ADC_CR_ADCAL & ADC_CR_ADCAL_Msk != 0) {}
/******************ADC clock*****************************/
SET_BIT(ADC12_COMMON->CCR, ADC_CCR_CKMODE_0 | ADC_CCR_CKMODE_1);
/*******************ADC Prescaler************************/
SET_BIT(ADC12_COMMON->CCR, ADC_CCR_PRESC_0 | ADC_CCR_PRESC_1 );
/*******************Input Mode***************************/
CLEAR_BIT(ADC1->DIFSEL, ADC_DIFSEL_DIFSEL_0); //Single Ended
/*******************ADC Enable***************************/
SET_BIT(ADC1->ISR, ADC_ISR_ADRDY_Msk);
SET_BIT(ADC1->CR, ADC_CR_ADEN_Msk);
while (ADC_ISR_ADRDY & ADC_ISR_ADRDY_Msk != 1) {}
SET_BIT(ADC1->ISR, ADC_ISR_ADRDY_Msk);
/********************ADC RES*****************************/
//SET_BIT(ADC1->CFGR, ADC_CFGR_RES_2 | ADC_CFGR_RES_1);
CLEAR_BIT(ADC1->CFGR, ADC_CFGR_RES_0 | ADC_CFGR_RES_1 | ADC_CFGR_RES_2);
/********************ADC Data Management*****************/
SET_BIT(ADC1->CFGR, ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1);//DMA Circular mode
/********************OVRMODE*****************************/
SET_BIT(ADC1->CFGR, ADC_CFGR_OVRMOD_Msk); //Erase old data
/*******************RSHIFT****************************/
SET_BIT(ADC1->CFGR2, ADC_CFGR2_RSHIFT1_Msk | ADC_CFGR2_RSHIFT2_Msk | ADC_CFGR2_RSHIFT3_Msk | ADC_CFGR2_RSHIFT4_Msk);
/********************CONT/Single/Discont*****************/
CLEAR_BIT(ADC1->CFGR, ADC_CFGR_DISCEN_Msk); // discontinuous mode
CLEAR_BIT(ADC1->CFGR, ADC_CFGR_CONT_Msk); // | ADC_CFGR_DISCEN_Msk
SET_BIT(ADC1->SQR1,ADC_SQR1_L_0 | ADC_SQR1_SQ2_4);
/********************Trigger Detection*******************/
SET_BIT(ADC1->CFGR, ADC_CFGR_EXTEN_0 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_3);//Trig rising edge TRGO2
CLEAR_BIT(ADC1->CFGR, ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTSEL_0 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_4);
/********************INput Preselection******************/
SET_BIT(ADC1->PCSEL, ADC_PCSEL_PCSEL_0 | ADC_PCSEL_PCSEL_16);//Chan 1
/********************Sample Time reg*********************/
SET_BIT(ADC1->SMPR1, ADC_SMPR1_SMP0_0 | ADC_SMPR1_SMP0_1 | ADC_SMPR1_SMP0_2); //2.5 CLCK Cycles
SET_BIT(ADC1->SMPR2, ADC_SMPR2_SMP16_0 | ADC_SMPR2_SMP16_1 | ADC_SMPR2_SMP16_2);
/********************ADC IT******************************/
// SET_BIT(ADC1->IER, ADC_IER_EOCIE_Msk | ADC_IER_EOSMPIE_Msk );//| ADC_IER_EOSIE_Msk | ADC_IER_OVRIE_Msk
// NVIC_EnableIRQ(ADC_IRQn);
// NVIC_SetVector(ADC_IRQn, (uint32_t)&ADC_IRQHandler);
}Here is the code I use to read within a sequence the data from ADC1 chan 0 and ADC1 chan 16 with chan 0 being read before chan 16. However the data received from the ADC is just a copy of the data from chan 0. Here is a picture of what I read (red trace is chan 0 and white trace is chan 16), what is disturbing here is that there is no signal input on the pin linked to the channel 16! (I use DMA to manage the data could it be a part of my problem?)
