Posted on January 09, 2015 at 10:36Hello.
I am programming RTC function including time/date and backup SRAM with STM32F407VG.
There is a 3.3V battery on the Vbat and a 32.768KHz xtal in my boards.
But there are very strange operations in my board.
When I enable both the RTC and the backup regulator, the backup SRAM contents are not retained when power is off.
(The RTC is working very well (Time is going well))
When I disable the RTC and enable the backup regulator, the backup SRAM contents are retained well when power is off.
Strangely, some board are working very well without the above problem.
The followings are source code.
Thank you in advance.
#define BDCR_SETUP_MASK 0x00008301 /* RTCEN, RTCSEL[1:0], LSEON */
#define BDCR_SETUP_CMP 0x00008101 /* RTCEN 1, RTCSEL 1, LSEON 1 */
void init_rtc(void)
{
RCC_APB1ENR |= (1 << 28); /* Power interface clock enable */
PWR_CR |= (1 << 8); /* disable backup domain write protection */
/* RTC, backup SRAM */
RCC_AHB1ENR |= (1 << 18); /* Backup SRAM interface clock enable */
if((RCC_BDCR & BDCR_SETUP_MASK) != BDCR_SETUP_CMP)
{
debug_out(''rtc: BDCR %08x, init backup domain\r\n'', RCC_BDCR);
RCC_BDCR |= (1 << 16); /* reset backup domain */
RCC_BDCR = 0; /* release reset */
RCC_BDCR |= (1 << 8); /* RTC clock source selection : LSE */
RCC_BDCR |= (1 << 0); /* switch on LSE oscillator */
while(!(RCC_BDCR & (1 << 1)))
; /* wait for LSE oscillator ready */
RCC_BDCR |= (1 << 15); /* RTC clock enable */
}
if(!(PWR_CSR & (1 << 9)))
{
debug_out(''rtc: init backup regulator\r\n'');
PWR_CSR |= (1 << 9); /* enable backup regulator for backup SRAM */
/* this bit is cleared by backup domain reset */
while(!(PWR_CSR & (1 << 3)))
; /* wait for Backup regulator ready */
}
}
