back-to-back write to the same FSMC address

[gordon239955]

Hi,

In my design, STM32F7 MCU communicates with FPGA via FSMC bus. FPGA emulates an asynchronous NOR flash. It was noticed that when MCU does back-to-back writes (2 lines of assembly code for each write) to the same FSMC address only the last 16-bit word appears on the FSMC bus. It seems that the first few writes are optimized away. I did check the assembly code and it looks correct. Can you advise on this?

Regards

Gordon

[Tesla DeLorean]

Perhaps write buffers, or caching?

Perhaps change the MPU configuration for the address space the FPGA lives in, so all writes reflect, and it's not treated as a memory device.

https://www.st.com/resource/en/application_note/dm00272912-managing-memory-protection-unit-in-stm32-mcus-stmicroelectronics.pdf