Anyone got the eMMC on the STM32L4P5G-DK reading over 33 MBps (8-bit DDR) ?

[Tesla DeLorean]

https://www.st.com/en/evaluation-tools/stm32l4p5g-dk.html

Clocking at 52 MHz 8-bit DDR mode, should be able to get a lot closer to 104 MBps, trying to decide if it is the card or the bus/peripheral getting in the way.

Also not impressed by the write speed either, but more frustrated with the bottleneck on the read, specs suggest it should go a lot faster.

[Tesla DeLorean]

eMMC speed demo, interaction via VCP at 115200 8N1

Integrity check will fill 4GB medium with multiple 650MB files containing pseudo-random data patterns, not sector/cluster aligned

Writes at about 4 MBps and Reads at around 35 MBps

[waclawek.jan]

> trying to decide if it is the card or the bus/peripheral getting in the way.

I know exactly zero about eMMC, but couldn't these two cases be distinguished by decreasing the peripheral's clock? If the performance won't change significantly, then it's the eMMC.

Observing the bus directly is impossible, I presume, given both parts are BGA?

JW

[Tesla DeLorean]

Dialled a lot of knobs on the clocking side (sources, ratios, cpu, sdmmc, etc), learned a few things that aren't well documented and not reflected in the library/bsp source.

Suspect it is pacing controlled by the Micron part, but not sure what settings/sequences unlock the speed.

DDR should double the throughput, even doubling CLKCR doesn't improve things.

The part seems to be self clocking or aware, as the input clock changing doesn't move the needle the way it might be expected.

[waclawek.jan]

> The part seems to be self clocking

There's a beefy controller inside, would you expect it to be otherwise?

Does its DS make any promises as per true readout speed (i.e. not bus clock speed)?

JW

PS

> learned a few things that aren't well documented and not reflected in the library/bsp source.

Sounds like you're having quality fun time :-)

[Tesla DeLorean]

>>There's a beefy controller inside, would you expect it to be otherwise?

Probably a lot of state machine / data path logic stuff bolted to an 8051/251 on steroids.. I guess I could hope its an ARM, MIPS, or SPARC, but not holding my breath.

JY976

MTFC4GACAJCN-1M WT

The spec of 14 / 90 MBps for the DDR52 Write/Read are about 3x what the STM32L+ is pulling out of it.

Missing the exact JEDEC JESD84-B50 incantations for the magic to happen

Mouser says the part is EOL, so buring some stock here. Would have preferred a SanDisk part.

[waclawek.jan]

> Mouser says the part is EOL

This kind of parts tends to be EOL before they hit the street. I'd hate to have to work with them.

> Missing the exact JEDEC JESD84-B50 incantations for the magic to happen

This too.

JW

[Tesla DeLorean]

Relatively low capacity parts in today's terms, thankfully the foot-print and command set are pinned down by JEDEC