AHB and APB

[idrissmc]

Hi ST Community,

I’d like to know why sometimes we use GPIO with AHB and sometimes with APB ?

[Tesla DeLorean]

Different designs have different goals and make different choices about how the buses and IP are connected.

You're probably overthinking this too much. ST is unlikely to review the history of design choices with you.

[waclawek.jan]

... and sometimes through a bus private to the processor, IOPORT (in Cortex-M0+).

JW

[idrissmc]

Yea but why it changes from an architecture to another? There’s necessarily an object

[waclawek.jan]

As Clive said, we can only guess.

Only in 'F1 is GPIO on APB. Then, I guess, influential (big-$) customers complained that they can't toggle GPIO outputs fast enough, so they moved in onto AHB.

IOPORT is only on Cortex-M0+ and it's ARM's invention/recommendation. It's fast, but it prevents accesses from other masters (e.g. DMA).

Even if you'd know for sure, why is it so, what would you do with that information?

JW